Icestorm: CCMP (immediate, 32-bit) measurements

Code:

  ccmp w1, #3, #0, hi

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  ccmp w1, #3, #0, hi
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519339	20108	20216	30221	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 2->2

Code:

  ccmp w0, #3, #0, hi

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10212	254709	10208	10208	20224	10101	100
10204	10030	10201	10201	10211	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10205	10060	10217	10217	10253	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	255150	10028	10032	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7891

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160206	63322	160188	160188	0	160193	688331	160118	160220	160216	160011	100
160204	63154	160112	160112	0	160118	689272	160120	160220	160218	160011	100
160204	63109	160110	160110	0	160115	689378	160118	160220	160216	160011	100
160204	63133	160115	160115	0	160120	691091	160124	160226	160220	160013	100
160204	63091	160112	160112	0	160118	688408	160160	160262	160220	160015	100
162282	76987	161916	161233	683	161184	689313	160121	160222	160224	160017	100
160204	63176	160112	160112	0	160118	686358	160118	160220	160220	160012	100
160204	63123	160112	160112	0	160118	687496	160115	160216	160220	160014	100
160204	63144	160115	160115	0	160120	687496	160115	160216	160220	160012	100
160204	63176	160112	160112	0	160118	688458	160120	160224	160220	160014	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7887

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64602	160035	160035	0	160039	0	696058	0	0	160042	160044	0	0	160020	160011	10
160024	63365	160021	160021	0	160020	0	697468	0	0	160020	160020	0	0	160020	160011	10
160024	63087	160021	160021	0	160020	0	695438	0	0	160020	160020	0	0	160020	160011	10
160024	63084	160021	160021	0	160020	0	689914	0	0	160020	160020	0	0	160020	160011	10
160024	63051	160021	160021	0	160020	0	696900	0	0	160020	160020	0	0	160020	160011	10
160024	63097	160021	160021	0	160020	0	692652	0	0	160020	160020	0	0	160020	160011	10
160024	63127	160021	160021	0	160020	0	697520	0	0	160020	160020	0	0	160020	160011	10
160024	63066	160021	160021	0	160020	0	698400	0	0	160020	160020	0	0	160020	160011	10
160024	63067	160021	160021	0	160020	0	695287	0	0	160020	160020	0	0	160020	160011	10
160024	63110	160021	160021	0	160020	0	694137	0	0	160020	160020	0	0	160020	160011	10

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24006	50110	40107	10003	40117	10005	315176	40013	50112	40209	10003	80232	20008	40005	100
50204	24004	50106	40103	10003	40112	10004	315036	40012	50112	40209	10003	80232	20008	40005	100
50204	23990	50103	40101	10002	40109	10003	315086	40018	50116	40212	10004	80232	20008	40007	100
50204	23985	50106	40103	10003	40109	10003	315036	40012	50112	40209	10003	80228	20008	40003	100
50204	23995	50104	40101	10003	40109	10003	315223	40018	50116	40212	10004	80228	20008	40003	100
50204	23987	50105	40102	10003	40112	10004	315434	40017	50116	40212	10004	80224	20008	40001	100
50204	23983	50103	40101	10002	40109	10003	315070	40013	50112	40209	10003	80298	20026	40029	100
50204	23993	50103	40101	10002	40109	10003	315528	40012	50114	40211	10003	80218	20006	40002	100
50204	23979	50104	40101	10003	40109	10003	315302	40013	50112	40209	10003	80218	20006	40003	100
50204	24013	50104	40101	10003	40112	10004	315449	40012	50112	40209	10003	80224	20008	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5996

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50025	24160	50051	40041	10010	40054	10011	0	316063	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23996	50011	40011	10000	40010	10000	0	316685	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	24006	50011	40011	10000	40010	10000	0	315631	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23959	50011	40011	10000	40010	10000	0	316679	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23959	50011	40011	10000	40010	10000	0	316377	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23975	50011	40011	10000	40010	10000	0	317393	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23974	50011	40011	10000	40010	10000	0	316877	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23985	50011	40011	10000	40010	10000	0	317393	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23975	50011	40011	10000	40010	10000	0	316679	0	40000	50010	40020	0	10000	80020	20000	40001	10
50024	23975	50011	40011	10000	40010	10000	0	316748	0	40000	50010	40020	0	10000	80020	20000	40001	10

Test 6: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi
  ccmp w0, #3, #0, hi

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5569

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39028	80107	80107	80116	549212	80111	80212	140238	80010	100
80205	39009	80134	80134	80151	548332	80111	80212	140228	80007	100
80204	38919	80106	80106	80116	548113	80116	80216	140220	80003	100
80204	38962	80103	80103	80114	549992	80111	80212	140228	80004	100
80204	39032	80107	80107	80116	549837	80111	80212	140228	80004	100
80204	38967	80107	80107	80116	549608	80111	80212	140228	80007	100
80204	39003	80104	80104	80111	548458	80114	80216	140228	80005	100
80204	38970	80103	80103	80108	550877	80116	80216	140228	80004	100
80204	38969	80103	80103	80111	549196	80116	80216	140228	80008	100
80204	39004	80103	80103	80111	549512	80114	80216	140214	80003	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5562

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	39193	80034	80034	80042	0	549821	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38905	80021	80021	80020	0	549663	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38924	80021	80021	80020	0	549044	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38917	80021	80021	80020	0	551785	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38954	80021	80021	80020	0	549391	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38926	80021	80021	80020	0	548624	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38927	80021	80021	80020	0	549172	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38915	80021	80021	80020	0	551960	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38922	80021	80021	80020	0	549172	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10
80024	38915	80021	80021	80020	0	549172	0	0	80020	80020	0	0	140020	0	0	80011	0	0	10

CCMP (immediate, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations