Icestorm: UDIV (fast, 32-bit) measurements

Code:

  udiv w0, w1, w2

Initialization

  mov w1, #0
  mov w2, #0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000
1004	7030	2001	2001	1000	61748	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv w0, w1, w2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	90030	40201	40201	30203	2398635	30203	30210	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398853	30234	30250	60220	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398677	30203	30210	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30206	90090	40212	40212	30264	2398718	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	90030	40011	40011	30013	2398954	30013	30030	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30027	90120	40030	40030	30107	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	30010	2398977	30010	30020	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv w0, w1, w2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	90030	40201	40201	30203	2398676	30203	30210	60224	40101	30100
30205	90061	40206	40206	30233	2398677	30203	30210	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2399075	30233	30252	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100
30204	90030	40201	40201	30203	2398718	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	90030	40011	40011	0	0	30013	0	2398935	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2398977	30010	30020	60642	40085	30010
30025	90060	40018	40018	0	0	30045	0	2398935	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2398977	30010	30020	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2399344	30043	30072	60020	40001	30010
30024	90030	40011	40011	0	0	30010	0	2398977	30010	30020	60020	40001	30010

Test 4: throughput

Code:

  udiv w0, w1, w2

Initialization

  mov w1, #0
  mov w2, #0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	70030	20101	20101	0	0	10100	0	620048	10100	10206	20212	20001	10100
10204	70204	20127	20127	0	0	10146	0	620048	10100	10208	20216	20001	10100
15001	90605	24480	22721	60	1699	12606	46	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	0	0	10100	0	620724	10144	10282	20216	20001	10100
10204	70030	20101	20101	0	0	10100	0	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	0	0	10100	0	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	0	0	10100	0	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	0	0	10100	0	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	0	0	10100	0	620048	10100	10208	20216	20001	10100
10204	70030	20101	20101	0	0	10100	0	620048	10100	10208	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 7.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10025	70060	20025	20025	10030	0	619808	0	10020	10026	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20068	20015	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010
10024	70030	20021	20021	10020	0	619808	0	10020	10020	0	20020	20011	10010

UDIV (fast, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations