Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

AUTDZA

Test 1: uops

Code:

  autdza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->1

Code:

  autdza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100
10204	60029	10201	10201	0	10200	530325	10200	200	200	0	0	10101	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10014	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010

Test 3: throughput

Count: 8

Code:

  autdza x0
  autdza x1
  autdza x2
  autdza x3
  autdza x4
  autdza x5
  autdza x6
  autdza x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	160030	80201	80201	80202	1360379	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360537	80220	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360566	80219	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360430	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360588	80220	200	200	0	0	80101	0	0	80100
80205	160064	80213	80213	80222	1360481	80202	200	200	0	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	0	80101	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	80022	1360048	80040	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1360026	80039	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80025	160064	80031	80031	80040	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010