Icestorm: PACGA measurements

Code:

  pacga x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->2

Code:

  pacga x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10004	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100
10204	60029	10101	10101	10100	530025	10100	200	200	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010

Test 3: Latency 1->3

Code:

  pacga x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10004	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100
10204	60029	10101	10101	10100	530025	10100	200	200	0	10001	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10014	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010
10024	60029	10021	10021	10020	0	529785	0	0	10020	20	0	0	20	10011	10010

Test 4: throughput

Count: 8

Code:

  pacga x0, x8, x9
  pacga x1, x8, x9
  pacga x2, x8, x9
  pacga x3, x8, x9
  pacga x4, x8, x9
  pacga x5, x8, x9
  pacga x6, x8, x9
  pacga x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	160030	80101	80101	80101	1360093	80101	200	200	80001	80100
80204	160030	80101	80101	80101	1360135	80101	200	200	80001	80100
80204	160030	80101	80101	80101	1360177	80101	200	200	80001	80100
80205	160060	80109	80109	80118	1360177	80101	200	200	80001	80100
80204	160030	80101	80101	80101	1360177	80101	200	200	80001	80100
80204	160030	80101	80101	80101	1360262	80118	200	200	80001	80100
80204	160030	80101	80101	80101	1360177	80101	200	200	80011	80100
80204	160030	80101	80101	80101	1360177	80101	200	200	80001	80100
80204	160030	80101	80101	80101	1360177	80101	200	200	80001	80100
80204	160030	80101	80101	80101	1360328	80120	200	200	80001	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	0	80022	1359880	80020	20	20	80011	80010
80024	160030	80021	80021	0	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	80020	1359931	80020	20	20	80020	80010
80024	160030	80021	80021	0	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	80020	1360040	80040	20	20	80021	80010
80024	160030	80021	80021	0	80020	1359931	80020	20	20	80011	80010
80025	160064	80031	80031	0	80040	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	0	80020	1360026	80039	20	20	80011	80010

PACGA

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations