Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
swp w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 2.000
Issues: 2.000
Integer unit issues: 0.001
Load/store unit issues: 2.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 72005 | 34417 | 2005 | 1 | 2004 | 2000 | 11767 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72005 | 34351 | 2003 | 1 | 2002 | 2000 | 11760 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34411 | 2001 | 1 | 2000 | 2000 | 11760 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34698 | 2001 | 1 | 2000 | 2000 | 11770 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34531 | 2001 | 1 | 2000 | 2000 | 11762 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34131 | 2001 | 1 | 2000 | 2000 | 11760 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34155 | 2001 | 1 | 2000 | 2000 | 11760 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34130 | 2001 | 1 | 2000 | 2000 | 11760 | 2000 | 2000 | 4004 | 1 | 2000 |
| 72004 | 34130 | 2001 | 1 | 2000 | 2000 | 11760 | 2000 | 2000 | 4000 | 1 | 2000 |
| 72004 | 34131 | 2001 | 1 | 2000 | 2000 | 11760 | 2000 | 2000 | 4000 | 1 | 2000 |
Code:
swp w0, w1, [x6] add x6, x6, 4
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0062
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30208 | 30798 | 30272 | 10169 | 20103 | 10169 | 20006 | 32894 | 126250 | 30109 | 10203 | 20007 | 10203 | 40013 | 10003 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32891 | 126396 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32891 | 126256 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32891 | 126388 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32891 | 126278 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32888 | 126177 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32888 | 126277 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32888 | 126283 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32888 | 126311 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
| 30204 | 30062 | 30105 | 10102 | 20003 | 10102 | 20005 | 32888 | 126311 | 30107 | 10202 | 20006 | 10202 | 40012 | 10002 | 20000 | 10100 |
Result (median cycles for code): 3.0058
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 30029 | 30715 | 30237 | 10097 | 20140 | 10097 | 20005 | 32625 | 127388 | 30017 | 10022 | 20006 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32592 | 127161 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32606 | 127541 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32592 | 127347 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32592 | 127251 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32592 | 127481 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32592 | 127511 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32592 | 127267 | 30010 | 10020 | 20000 | 10043 | 40096 | 10023 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32616 | 127561 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
| 30024 | 30058 | 30011 | 10011 | 20000 | 10010 | 20000 | 32614 | 127385 | 30010 | 10020 | 20000 | 10020 | 40000 | 10001 | 20000 | 10010 |
Code:
swp w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 10.4799
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20205 | 101333 | 20136 | 101 | 20035 | 100 | 20000 | 500 | 1797223 | 20100 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 101326 | 20102 | 101 | 20001 | 100 | 20066 | 500 | 1779970 | 20166 | 200 | 20100 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 100080 | 20101 | 101 | 20000 | 100 | 20000 | 500 | 1779129 | 20100 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 100080 | 20101 | 101 | 20000 | 100 | 20000 | 500 | 1779129 | 20100 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 100080 | 20101 | 101 | 20000 | 100 | 20000 | 500 | 1779129 | 20100 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 100080 | 20101 | 101 | 20000 | 100 | 20000 | 500 | 1779129 | 20100 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 100086 | 20101 | 101 | 20000 | 100 | 20000 | 500 | 1779129 | 20100 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 100080 | 20101 | 101 | 20000 | 100 | 20000 | 500 | 1779129 | 20100 | 200 | 20004 | 200 | 40008 | 1 | 20000 | 100 |
| 20204 | 100080 | 20101 | 101 | 20000 | 100 | 20184 | 500 | 1801698 | 20284 | 200 | 20430 | 200 | 40828 | 1 | 20000 | 100 |
| 20204 | 104678 | 20179 | 101 | 20078 | 100 | 20019 | 500 | 1859121 | 20119 | 200 | 20052 | 200 | 40160 | 1 | 20000 | 100 |
Result (median cycles for code): 10.0217
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20026 | 100612 | 20131 | 11 | 20120 | 10 | 20000 | 50 | 1781143 | 20010 | 20 | 20004 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 100192 | 20011 | 11 | 20000 | 10 | 20000 | 50 | 1781143 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20025 | 100136 | 20058 | 11 | 20047 | 10 | 20000 | 50 | 1782114 | 20010 | 20 | 20000 | 20 | 40000 | 1 | 20000 | 10 |
| 20024 | 100169 | 20011 | 11 | 20000 | 10 | 20000 | 50 | 1779003 | 20010 | 20 | 20000 | 20 | 40160 | 1 | 20000 | 10 |
| 20024 | 100266 | 20020 | 11 | 20009 | 10 | 20016 | 50 | 1781461 | 20026 | 20 | 20048 | 20 | 40024 | 1 | 20000 | 10 |
| 20024 | 100310 | 20014 | 11 | 20003 | 10 | 20004 | 50 | 1783248 | 20014 | 20 | 20012 | 20 | 40024 | 1 | 20000 | 10 |
| 20024 | 100310 | 20014 | 11 | 20003 | 10 | 20029 | 49 | 1783263 | 20039 | 20 | 20078 | 20 | 40156 | 1 | 20000 | 10 |
| 20024 | 100425 | 20026 | 11 | 20015 | 10 | 20032 | 50 | 1789034 | 20042 | 20 | 20088 | 20 | 40388 | 1 | 20000 | 10 |
| 20024 | 100497 | 20067 | 11 | 20056 | 10 | 20049 | 50 | 1785666 | 20059 | 20 | 20128 | 20 | 40140 | 1 | 20000 | 10 |
| 20024 | 100365 | 20049 | 11 | 20038 | 10 | 20017 | 49 | 1790960 | 20027 | 20 | 20046 | 20 | 40140 | 1 | 20000 | 10 |