Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
casal x0, x1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 4.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 74007 | 35154 | 3010 | 1 | 3009 | 3000 | 15035 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34783 | 3001 | 1 | 3000 | 3000 | 15039 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34575 | 3001 | 1 | 3000 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34765 | 3001 | 1 | 3000 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 35455 | 3001 | 1 | 3000 | 3000 | 15104 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 35134 | 3001 | 1 | 3000 | 3000 | 15034 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34620 | 3001 | 1 | 3000 | 3000 | 15032 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34477 | 3001 | 1 | 3000 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34540 | 3001 | 1 | 3000 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
| 74004 | 34455 | 3001 | 1 | 3000 | 3000 | 15033 | 3000 | 1000 | 3000 | 1000 | 6000 | 1 | 3000 | 1000 |
Code:
casal x0, x1, [x6] add x6, x6, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 9.0060
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 50214 | 90550 | 41906 | 11807 | 30099 | 11802 | 30036 | 36531 | 355679 | 42178 | 20223 | 30036 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355484 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355484 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355484 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355486 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355465 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90060 | 44268 | 14267 | 30001 | 14265 | 30036 | 38770 | 355744 | 42921 | 20223 | 30036 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355484 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355484 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
| 50204 | 90058 | 44269 | 14268 | 30001 | 14265 | 30003 | 42887 | 355484 | 44268 | 20201 | 30003 | 20201 | 60006 | 14168 | 30000 | 20100 |
Result (median cycles for code): 9.0051
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 50034 | 90534 | 41814 | 11715 | 30099 | 11712 | 30003 | 42617 | 355746 | 44178 | 20021 | 30003 | 20021 | 60006 | 14169 | 30000 | 20010 |
| 50024 | 90058 | 44178 | 14178 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
| 50024 | 90051 | 44177 | 14177 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
| 50024 | 90051 | 44177 | 14177 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
| 50024 | 90051 | 44177 | 14177 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20043 | 60072 | 13912 | 30000 | 20010 |
| 50024 | 90058 | 44178 | 14178 | 30000 | 14175 | 30000 | 42587 | 355586 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
| 50024 | 90051 | 44177 | 14177 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
| 50024 | 90051 | 44177 | 14177 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
| 50024 | 90051 | 44177 | 14177 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
| 50024 | 90051 | 44177 | 14177 | 30000 | 14175 | 30000 | 42592 | 355629 | 44175 | 20020 | 30000 | 20020 | 60000 | 14167 | 30000 | 20010 |
Code:
casal x0, x1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 24.0039
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 40205 | 240126 | 38449 | 8432 | 0 | 30017 | 4269 | 0 | 30003 | 920646 | 2938435 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8311 | 30000 | 0 | 10100 |
| 40204 | 240046 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40205 | 240098 | 35505 | 5475 | 0 | 30030 | 2800 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240039 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240039 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10212 | 60072 | 0 | 3778 | 30000 | 0 | 10100 |
| 40204 | 240039 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240042 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10214 | 60072 | 0 | 7702 | 30000 | 0 | 10100 |
| 40205 | 240072 | 37049 | 7019 | 0 | 30030 | 3574 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240039 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8297 | 30000 | 0 | 10100 |
| 40204 | 240039 | 38398 | 8397 | 0 | 30001 | 4265 | 0 | 30003 | 920637 | 2938357 | 0 | 34268 | 10201 | 30003 | 0 | 10201 | 60006 | 0 | 8330 | 30000 | 0 | 10100 |
Result (median cycles for code): 24.0046
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 40029 | 240299 | 33418 | 3345 | 30073 | 1682 | 30036 | 551742 | 2939132 | 32543 | 10032 | 30036 | 10021 | 60006 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38340 | 8339 | 30001 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10027 | 60030 | 8330 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30036 | 750036 | 2938787 | 33442 | 10032 | 30036 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10020 | 60000 | 8329 | 30000 | 10010 |
| 40025 | 240114 | 35272 | 5242 | 30030 | 2631 | 30000 | 920388 | 2938554 | 34175 | 10020 | 30000 | 10032 | 60072 | 6908 | 30000 | 10010 |
| 40024 | 240046 | 38339 | 8339 | 30000 | 4175 | 30003 | 920380 | 2938546 | 34178 | 10021 | 30003 | 10020 | 60000 | 8330 | 30000 | 10010 |