Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CRC32W

Test 1: uops

Code:

  crc32w w0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002595910141022200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000

Test 2: Latency 1->2

Code:

  crc32w w0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
102043003010101101010101002601501010010206202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002601561010010208202161000110100
102043003010101101010101002602591011410228202161000110100
102043003010101101010101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202598981002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202600701003510041200201001110010
10024300301002110021100202599161002010020200201001110010

Test 3: Latency 1->3

Code:

  crc32w w0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601441010010206202121000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002602591011410229202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599161002010028200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200761001610010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010

Test 4: throughput

Count: 8

Code:

  crc32w w0, w8, w9
  crc32w w1, w8, w9
  crc32w w2, w8, w9
  crc32w w3, w8, w9
  crc32w w4, w8, w9
  crc32w w5, w8, w9
  crc32w w6, w8, w9
  crc32w w7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802048005480104801048010524031580105802101602208000480100
802058006680120801208012424031580105802101602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524042380143802641602248000480100
802048003480104801048010524031580105802101602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100
802048003480104801048010524031580105802121602248000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800258006780041800418004524007880026800341600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800278013180073800738008324013280045800591600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010