Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PACDZA

Test 1: uops

Code:

  pacdza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52825	1011	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->1

Code:

  pacdza x0

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10205	60058	10204	10204	10211	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10101	0	0	10100
10204	60029	10201	10201	10200	530325	10200	200	200	0	10104	0	0	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	61798	10193	10193	0	0	10528	0	537129	10596	20	22	0	0	10184	0	0	10010
10024	61883	10197	10197	0	0	10548	0	537288	10610	22	24	0	0	10189	0	0	10010
10024	62179	10221	10221	0	0	10620	0	536364	10536	20	4931	4106	179	9196	1493	81	9285
10024	61925	10201	10201	0	0	10560	0	537435	10620	20	20	0	0	10187	0	0	10010
10024	62096	10219	10219	0	0	10610	0	536525	10548	20	20	0	0	10187	0	0	10010
10024	62102	10217	10217	0	0	10608	0	536523	10550	22	20	0	0	10211	0	0	10010
10024	61928	10203	10203	0	0	10562	0	536676	10562	22	21	0	0	10211	0	0	10010
10024	61880	10198	10198	0	0	10549	0	537298	10608	20	24	0	0	10189	0	0	10010
10024	62055	10217	10217	0	0	10600	0	537435	10620	20	22	0	0	10188	0	0	10010
10024	62054	10215	10215	0	0	10598	0	536517	10548	20	23	0	0	10212	0	0	10010

Test 3: throughput

Count: 8

Code:

  pacdza x0
  pacdza x1
  pacdza x2
  pacdza x3
  pacdza x4
  pacdza x5
  pacdza x6
  pacdza x7

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	160030	80201	80201	80202	1360430	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80111	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360573	80220	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80111	80100
80204	160211	80250	80250	80275	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	80101	80100
80205	160064	80210	80210	80220	1360481	80202	200	200	80101	80100
80204	160030	80201	80201	80202	1360580	80220	200	200	80101	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	80022	0	1359941	0	80022	20	0	20	80011	80010
80025	160064	80031	80031	80040	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1360040	0	80040	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1360033	0	80040	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010
80024	160030	80021	80021	80020	0	1359931	0	80020	20	0	20	80011	80010