Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (immediate, 32-bit)

Test 1: uops

Code:

  cmp w0, #3

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	520	1001	1001	1000	3000	1000	1000	1000	1001
1004	398	1001	1001	1000	3000	1000	1000	1000	1001
1004	390	1001	1001	1000	3000	1000	1000	1000	1001
1004	392	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	391	1001	1001	1000	3000	1000	1000	1000	1001
1004	390	1001	1001	1000	3000	1000	1000	1000	1001
1004	393	1001	1001	1000	3000	1000	1000	1000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  cmp w0, #3
  cset x0, cc

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519442	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519507	20017	20032	20036	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	20020	20001	10010

Test 3: throughput

Count: 8

Code:

  cmp w0, #3
  cmp w0, #3
  cmp w0, #3
  cmp w0, #3
  cmp w0, #3
  cmp w0, #3
  cmp w0, #3
  cmp w0, #3

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29227	80113	80113	80118	240351	80117	80220	80220	80015	100
80204	29237	80153	80153	80157	240354	80118	80220	80220	80013	100
80204	29039	80115	80115	80119	240360	80120	80220	80220	80013	100
80204	29128	80115	80115	80120	240360	80120	80220	80220	80013	100
80204	29121	80113	80113	80118	240351	80117	80220	80220	80015	100
80204	29081	80154	80154	80158	240357	80119	80220	80332	80126	100
80204	29298	80232	80232	80236	240588	80196	80298	80220	80013	100
80204	29406	80270	80270	80274	240468	80156	80258	80220	80012	100
80204	29095	80113	80113	80118	240351	80117	80220	80220	80015	100
80204	29341	80230	80230	80234	240357	80119	80220	80220	80013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
82178	45391	82128	81315	813	81282	240119	80039	80040	80020	80011	10
80024	29095	80021	80021	0	80020	240062	80020	80020	80020	80011	10
80024	28981	80021	80021	0	80020	240070	80020	80020	80020	80011	10
80025	29129	80072	80072	0	80076	240061	80020	80020	80020	80011	10
80024	29000	80021	80021	0	80020	240074	80020	80020	80020	80011	10
80024	28963	80021	80021	0	80020	240066	80020	80020	80020	80011	10
80024	29019	80021	80021	0	80020	240067	80020	80020	80020	80011	10
80024	28940	80021	80021	0	80020	240079	80020	80020	80020	80011	10
80024	29108	80021	80021	0	80020	240080	80020	80020	80020	80011	10
80024	29043	80021	80021	0	80020	240070	80020	80020	80020	80011	10