Icestorm: BICS (register, 64-bit) measurements

Code:

  bics x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  bics x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10109	251671	10109	10210	20216	10001	10100
10204	10030	10101	10101	10109	252105	10148	10248	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	0	0	10028	0	0	253292	0	0	10028	10030	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010
10024	10030	10021	10021	0	0	10020	0	0	253161	0	0	10020	10020	0	0	20020	10011	10010

Test 3: Latency 1->3

Code:

  bics x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	251641	10106	10206	20220	10001	10100
10204	10030	10101	10101	10108	251641	10109	10210	20220	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	253256	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  bics x0, x1, x2
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519197	20108	20214	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20178	20074	20074	20142	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  bics x0, x1, x2
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519291	20107	20214	30221	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30290	20015	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010

Test 6: throughput

Count: 8

Code:

  bics x0, x8, x9
  bics x1, x8, x9
  bics x2, x8, x9
  bics x3, x8, x9
  bics x4, x8, x9
  bics x5, x8, x9
  bics x6, x8, x9
  bics x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	40081	80111	80111	80114	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40087	80112	80112	80115	240345	80115	80216	160232	80012	80100
80205	40106	80140	80140	80148	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100
80204	40081	80112	80112	80115	240345	80115	80216	160232	80012	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	40145	80032	80032	80035	240066	80020	80020	160020	80011	80010
80025	40071	80059	80059	80067	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240174	80053	80053	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010
80024	40030	80021	80021	80020	240065	80020	80020	160020	80011	80010

BICS (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations