Icestorm: LDRSB (post-index, 32-bit) measurements

Code:

  ldrsb w0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1231	2031	1018	1013	1036	1000	20761	17530	2000	1000	1000	1000	1000	1001	1000	1000
2004	1064	2001	1001	1000	1000	1000	20894	17797	2000	1000	1000	1000	1000	1001	1000	1000
2004	1070	2001	1001	1000	1000	1000	21011	17486	2000	1000	1000	1000	1000	1001	1000	1000
2004	1121	2001	1001	1000	1000	1000	21101	17534	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21060	17805	2000	1000	1000	1000	1000	1001	1000	1000
2004	1068	2001	1001	1000	1000	1000	21185	17660	2000	1000	1000	1000	1000	1001	1000	1000
2004	1116	2001	1001	1000	1000	1000	21074	17448	2000	1000	1000	1000	1000	1001	1000	1000
2004	1122	2001	1001	1000	1000	1000	21008	17681	2000	1000	1000	1000	1000	1001	1000	1000
2004	1127	2001	1001	1000	1000	1000	21111	18494	2000	1000	1000	1000	1000	1001	1000	1000
2004	1100	2001	1001	1000	1000	1000	21099	17376	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0147

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71254	50161	40156	10005	40247	10003	1850074	534582	50109	40212	10004	70221	10004	40005	10000	40100
50204	70101	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70180	50104	40104	10000	40106	10003	1850280	534709	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70289	10013	40015	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100
50204	70097	50104	40104	10000	40106	10003	1850118	534660	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0110

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71260	50070	40065	10005	40156	10003	1850802	535220	50019	40032	10004	70020	10000	40004	10000	40010
50025	70197	50027	40025	10002	40050	10000	1851254	535357	50010	40020	10000	70020	10000	40003	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70020	10000	40003	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70020	10000	40003	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70020	10000	40003	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70020	10000	40003	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70020	10000	40003	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70020	10000	40003	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70109	10013	40014	10000	40010
50024	70110	50013	40013	10000	40010	10000	1850525	535124	50010	40020	10000	70020	10000	40003	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsb w0, [x6], #8
  ldrsb w0, [x7], #8
  ldrsb w0, [x8], #8
  ldrsb w0, [x9], #8
  ldrsb w0, [x10], #8
  ldrsb w0, [x11], #8
  ldrsb w0, [x12], #8
  ldrsb w0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44265	160422	80312	80110	80315	80010	240610	637336	160122	80212	80012	80212	80012	80009	80000	80100
160204	43235	160109	80109	80000	80112	80011	240610	643803	160123	80212	80012	80212	80012	80009	80000	80100
160204	43232	160108	80107	80001	80108	80011	240610	642722	160123	80212	80012	80212	80012	80009	80000	80100
160204	43231	160109	80109	80000	80112	80012	240610	647050	160124	80212	80012	80212	80012	80009	80000	80100
160204	43231	160109	80109	80000	80112	80011	240610	640517	160123	80212	80012	80212	80012	80009	80000	80100
160204	43230	160107	80107	80000	80110	80011	240610	644907	160123	80212	80012	80212	80012	80009	80000	80100
160204	43230	160107	80107	80000	80110	80011	240610	639435	160123	80212	80012	80212	80012	80009	80000	80100
160204	43231	160109	80109	80000	80112	80011	240610	643206	160123	80212	80012	80212	80012	80009	80000	80100
160205	43301	160181	80151	80030	80154	80010	240714	627874	160122	80212	80012	80212	80012	80009	80000	80100
160204	43237	160109	80109	80000	80112	80011	240610	646631	160123	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44736	160344	80222	80122	80225	80012	240215	646027	160034	80032	80012	80020	80000	80001	80000	80010
160024	43216	160011	80011	80000	80010	80000	240179	647424	160010	80020	80000	80074	80054	80051	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	644191	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	642300	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	640686	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	643592	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	643595	160010	80020	80000	80020	80000	80001	80000	80010
160024	43219	160011	80011	80000	80010	80000	240179	641445	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	645494	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	643945	160010	80020	80000	80020	80000	80001	80000	80010

LDRSB (post-index, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations