Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRB

Test 1: uops

Code:

  ldrb w0, [x6]

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	652	1025	1	1024	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	550	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	546	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	1000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70524	40108	30107	10001	30130	10003	1859587	694038	40106	30212	10004	60224	10004	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70110	40102	30102	10000	30103	10003	1859662	694098	40106	30212	10004	60224	10004	30002	10000	30100
40204	70045	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10015	1859791	694135	40150	30247	10017	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	10004	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70155	40018	30017	10001	30040	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859652	694714	40010	30020	10000	60020	10000	30003	10000	30010

Test 3: throughput

Count: 8

Code:

  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]
  ldrb w0, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80205	40169	80129	101	80028	100	80008	300	248262	80108	200	80012	200	80012	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	0	1	80000	0	100
80204	40062	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	0	1	80000	0	100
80205	40108	80135	101	80034	100	80008	300	641600	80108	200	80012	3465	82166	15	1629	80876	9	1901
80204	40059	80101	101	80000	100	80008	300	640412	80108	200	80012	200	80012	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	0	1	80000	0	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	80012	0	1	80000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40337	80035	11	80024	10	80008	30	400298	80018	20	80012	20	80012	1	80000	10
80024	40049	80011	11	80000	10	80008	30	640142	80018	20	80012	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40165	80011	11	80000	10	80000	30	640472	80010	20	80000	20	80000	1	80000	10
80024	40055	80011	11	80000	10	80000	30	640274	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10
80024	40047	80011	11	80000	10	80000	30	640112	80010	20	80000	20	80000	1	80000	10