Icestorm: SDIV (slow, 64-bit) measurements

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0x8000000000000000
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000
1004	21030	2001	2001	1000	187244	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0x8000000000000000
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	230030	40201	40201	30203	6177150	30203	30210	60220	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177528	30234	30252	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177566	30230	30244	60298	40103	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60304	40104	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177542	30232	30248	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30025	230060	40014	40014	30042	6177453	30013	30030	60020	40001	30010
30025	230060	40013	40013	30041	6177815	30042	30068	60020	40001	30010
30025	230060	40014	40014	30042	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60116	40002	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177815	30042	30068	60020	40001	30010
30026	230090	40016	40016	30070	6177465	30010	30020	60020	40001	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	40001	30010
30025	230060	40012	40012	30037	6177465	30010	30020	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  sdiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0x8000000000000000
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	230030	40201	40201	30203	6177150	30203	30210	60224	40101	30100
30204	230030	40201	40201	30203	6177566	30230	30248	60224	40101	30100
30205	230060	40204	40204	30232	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60294	40102	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177523	30230	30245	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100
30204	230030	40201	40201	30203	6177206	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30025	230060	40012	40012	30040	6177484	30013	30032	60020	0	40001	0	0	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	0	40001	0	0	30010
30025	230060	40014	40014	30042	6177465	30010	30020	60114	0	40003	0	0	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60108	0	40002	0	0	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60122	0	40003	0	0	30010
30025	230060	40012	40012	30040	6177484	30013	30032	60020	0	40001	0	0	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	0	40001	0	0	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60116	0	40003	0	0	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	0	40001	0	0	30010
30024	230030	40011	40011	30010	6177465	30010	30020	60020	0	40001	0	0	30010

Test 4: throughput

Code:

  sdiv x0, x1, x2

Initialization

  mov x1, #0x8000000000000000
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	210030	20101	20101	10100	0	1879544	0	10100	10206	0	20212	20001	10100
10204	210030	20101	20101	10100	0	1879544	0	10100	10208	0	20216	20001	10100
10206	210090	20103	20103	10118	0	1879544	0	10100	10208	0	20216	20001	10100
10204	210030	20101	20101	10100	0	1879544	0	10100	10208	0	20216	20001	10100
10204	210030	20101	20101	10100	0	1879544	0	10100	10208	0	20216	20001	10100
10205	210060	20102	20102	10109	0	1879544	0	10100	10208	0	20216	20001	10100
10205	210060	20104	20104	10111	0	1879544	0	10100	10208	0	20216	20001	10100
10204	210030	20101	20101	10100	0	1879661	0	10109	10224	0	20216	20001	10100
10204	210030	20101	20101	10100	0	1879544	0	10100	10206	0	20216	20001	10100
10204	210030	20101	20101	10100	0	1879544	0	10100	10208	0	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 21.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	210030	20021	20021	0	0	10020	0	1879304	10020	10026	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879421	10029	10044	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879304	10020	10020	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879304	10020	10020	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879421	10029	10042	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879304	10020	10020	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879304	10020	10020	20020	20011	10010
10025	210060	20022	20022	0	0	10029	0	1879304	10020	10020	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879304	10020	10020	20020	20011	10010
10024	210030	20021	20021	0	0	10020	0	1879304	10020	10020	20020	20011	10010

SDIV (slow, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations