Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PSTL3STRM)

Test 1: uops

Code:

  prfm pstl3strm, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2115	1001	1	1000	1000	34904	1000	1000	1000	1	1000
1004	2099	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2098	1001	1	1000	1000	34914	1000	1000	1000	1	1000
1004	2098	1001	1	1000	1000	34892	1000	1000	1000	1	1000
1004	2098	1001	1	1000	1000	34906	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34928	1000	1000	1000	1	1000
1004	2108	1001	1	1000	1000	34786	1000	1000	1000	1	1000
1004	2105	1001	1	1000	1000	34924	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34936	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34910	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pstl3strm, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0176

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	21151	20102	10102	10000	10104	10006	61297	350653	20117	10213	10013	10213	10013	10007	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10204	10004	10003	10000	10100
20204	20039	20103	10103	10000	10102	10000	61256	350623	20100	10202	10002	10208	10008	10002	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10002	61447	349717	20110	10210	10010	10202	10002	10001	10000	10100
20204	19961	20103	10103	10000	10102	10002	61287	350185	20110	10210	10010	10208	10008	10002	10000	10100
20204	20083	20105	10105	10000	10108	10000	61454	350659	20100	10202	10002	10202	10002	10001	10000	10100
20204	20135	20101	10101	10000	10100	10000	61256	350623	20100	10202	10002	10202	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0169

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	22738	20017	10017	10000	10023	10000	60909	351399	20013	10025	10005	10020	10000	10001	10000	10010
20024	20346	20011	10011	10000	10013	10000	61041	351187	20010	10020	10000	10020	10000	10001	10000	10010
20024	20172	20011	10011	10000	10010	10000	60878	351429	20010	10020	10000	10020	10000	10001	10000	10010
20024	20171	20011	10011	10000	10010	10000	61079	350331	20010	10020	10000	10020	10000	10001	10000	10010
20024	20137	20011	10011	10000	10010	10000	61004	351339	20010	10020	10000	10020	10000	10001	10000	10010
20024	20072	20011	10011	10000	10010	10000	60918	352005	20010	10020	10000	10020	10000	10001	10000	10010
20024	20158	20011	10011	10000	10010	10000	60932	351087	20010	10020	10000	10020	10000	10001	10000	10010
20024	20235	20011	10011	10000	10010	10000	60633	350565	20010	10020	10000	10020	10000	10001	10000	10010
20024	20099	20011	10011	10000	10010	10000	60897	350487	20010	10020	10000	10020	10000	10001	10000	10010
20024	20158	20011	10011	10000	10010	10000	60938	351447	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pstl3strm, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0958

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20938	10101	101	10000	100	10006	300	365398	10106	200	10012	200	10012	1	10000	100
10204	20958	10101	101	10000	100	10006	300	365450	10106	200	10012	200	10012	1	10000	100
10204	20958	10101	101	10000	100	10006	300	365450	10106	200	10012	200	10012	1	10000	100
10204	20958	10101	101	10000	100	10006	300	365450	10106	200	10012	200	10012	1	10000	100
10204	20944	10101	101	10000	100	10000	300	365044	10100	200	10004	200	10004	1	10000	100
10204	20770	10101	101	10000	100	10000	300	360660	10100	200	10004	200	10012	1	10000	100
10204	20891	10101	101	10000	100	10000	300	364304	10100	200	10008	200	10004	1	10000	100
10204	20481	10101	101	10000	100	10006	300	363866	10106	200	10012	200	10004	1	10000	100
10204	20868	10101	101	10000	100	10000	300	363808	10100	200	10004	200	10008	1	10000	100
10204	20880	10101	101	10000	100	10000	300	356222	10100	200	10008	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.8731

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	19321	10011	11	10000	10	10004	30	331658	10014	20	10012	20	10000	1	10000	10
10024	19479	10011	11	10000	10	10000	30	339210	10010	20	10000	20	10000	1	10000	10
10024	19371	10011	11	10000	10	10000	30	333518	10010	20	10000	20	10000	1	10000	10
10024	19398	10011	11	10000	10	10000	30	338048	10010	20	10000	20	10000	1	10000	10
10024	19594	10011	11	10000	10	10000	30	336554	10010	20	10000	20	10000	1	10000	10
10024	19541	10011	11	10000	10	10000	30	333716	10010	20	10000	20	10000	1	10000	10
10024	19547	10011	11	10000	10	10000	30	338112	10010	20	10000	20	10000	1	10000	10
10024	19697	10071	11	10060	10	10000	30	338272	10010	20	10000	20	10000	1	10000	10
10024	19601	10011	11	10000	10	10000	30	335272	10010	20	10000	20	10000	1	10000	10
10024	19351	10011	11	10000	10	10000	30	325728	10010	20	10000	20	10000	1	10000	10