Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDPSW (signed offset)

Test 1: uops

Code:

  ldpsw x0, x1, [x6, #8]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
200567810211102010006478100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007290100020002000110001000
200455410011100010007164100020002000110001000
200454710011100010007164100020002000110001000

Test 2: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldpsw x0, x1, [x6, #8]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020570154401083010710001301301000318557817099554010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020570077401133011110002301371000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100
5020470047401033010310000301031000318584787110214010630212200086022420008300031000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002570156400183001710001300401000318595817121184001630032200086002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010
5002470047400133001310000300101000018589497119754001030020200006002020000300031000040010

Test 3: Latency 2->3 (with chain penalty)

Chain cycles: 3

Code:

  ldpsw x0, x1, [x6, #8]
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020570164401083010710001301301000318585527110074010630212200086022420008300021000040100
5020470040401023010210000301031001518602317117354015030250200346022420008300021000040100
5020470125401033010310000301031000318584787110564010630211200086022420008300031000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086030020034300101000040100
5020470049401033010310000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470042401023010210000301031000318583437109714010630212200086022420008300021000040100
5020470048401023010210000301031000318583437109714010630212200086022420008300021000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
50025701474001830017100013004010000185876071190540010300202000060098200263000810000040010
50024700474001330013100003001010000185876071190540010300202000060020200003000210000040010
50024700474001330013100003001010000185876071190540010300202000060020200003000210000040010
50024700474001330013100003001010000185876071190540010300202000060020200003000210000040010
50024700474001330013100003001010000185876071190540010300202000060020200003000210000040010
50024700474001330013100003001010000185876071190540010300202000060020200003000210000040010
50024700474001330013100003001010000185876071190540010300202000060020200003000210000040010
50024700474001330013100003001010000185876071190540010300202000060020200003000210000040010
50024700474001330013100003001010015185959671217740060300702003460020200003000210000040010
50024700514001330013100003001010000185876071190540010300202000060020200003000210000040010

Test 4: throughput

Count: 8

Code:

  ldpsw x0, x1, [x6, #8]
  ldpsw x0, x1, [x6, #8]
  ldpsw x0, x1, [x6, #8]
  ldpsw x0, x1, [x6, #8]
  ldpsw x0, x1, [x6, #8]
  ldpsw x0, x1, [x6, #8]
  ldpsw x0, x1, [x6, #8]
  ldpsw x0, x1, [x6, #8]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5012

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205403158013510180034100800123002452708011220016002420016002418000080100
160204401078010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002610808011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100
160204401058010910180008100800123002453688011220016002420016002418000080100
160204400988010910180008100800123002546008011220016002420016002418000080100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600254076680039118002810800123034436380022201600242016002418000080010
1600244007380011118000010800003024132280010201600002016000018000080010
1600244005980011118000010800553039402180065201601102016000018000080010
1600244005980011118000010800003025480480010201600002016000018000080010
1600244006180011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016000018000080010
1600244005780011118000010800003024346680010201600002016011218000080010