Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ORR (register, ror, 32-bit)

Test 1: uops

Code:

  orr w0, w0, w1, ror #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000

Test 2: Latency 1->2

Code:

  orr w0, w0, w1, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045291261010410210202202000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292761002510032200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010

Test 3: Latency 1->3

Code:

  orr w0, w1, w0, ror #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290661010410210202202000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212202242000110100
10204200302010120101101045291861010410212203062001610100
10204200302010120101101045291861010410212202242000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292201002510034201282002510010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010
10024200302002120021100205292531002010020200202001110010

Test 4: throughput

Count: 8

Code:

  orr w0, w8, w9, ror #17
  orr w1, w8, w9, ror #17
  orr w2, w8, w9, ror #17
  orr w3, w8, w9, ror #17
  orr w4, w8, w9, ror #17
  orr w5, w8, w9, ror #17
  orr w6, w8, w9, ror #17
  orr w7, w8, w9, ror #17
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8020453404160117160117801301360634801778028616026816001680100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100
8020453404160117160117801301360838801308023616027216001780100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002553412160088160088801001359718800518005816002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010
8002453371160021160021800201359903800208002016002016001180010