Icestorm: LDR (register, lsl, 64-bit) measurements

Code:

  ldr x0, [x6, x7, lsl #3]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	690	1021	1	1020	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000
1004	545	1001	1	1000	1000	8076	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7, lsl #3]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70153	40108	30107	10001	30130	10003	1859614	693951	40106	30210	10004	60220	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60224	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60224	20008	30003	10000	30100
40204	70051	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60224	20008	30003	10000	30100
40204	70054	40103	30103	10000	30103	10003	1859905	694192	40106	30212	10004	60224	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60224	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60294	20034	30009	10000	30100
40204	70076	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60224	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859662	694093	40106	30212	10004	60224	20008	30003	10000	30100
40204	70050	40103	30103	10000	30103	10003	1859689	694104	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0041

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70162	40018	30017	10001	30040	10003	1859704	693728	40016	30030	10004	60044	20008	30004	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70114	40013	30013	10000	30010	10000	1859814	694786	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7, lsl #3]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70160	40108	30107	10001	30130	10003	1859614	693951	40106	30210	10004	60220	20008	30003	10000	30100
40205	70159	40112	30110	10002	30135	10003	1859689	694106	40106	30212	10004	60220	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10015	1862194	695103	40150	30251	10017	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0043

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70149	40018	30017	10001	30040	10015	1861642	694494	40060	30069	10017	60040	20008	30003	10000	30010
40024	70048	40013	30013	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70041	40012	30012	10000	30010	10000	1859490	694654	40010	30020	10000	60020	20000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10000	1859517	694665	40010	30020	10000	60114	20034	30008	10000	30010
40024	70046	40012	30012	10000	30010	10003	1859779	694778	40016	30032	10004	60020	20000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10000	1859544	694674	40010	30020	10000	60020	20000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10000	1859544	694674	40010	30020	10000	60020	20000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10000	1859544	694674	40010	30020	10000	60020	20000	30002	10000	30010
40024	70043	40012	30012	10000	30010	10000	1859544	694674	40010	30020	10000	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40541	80137	101	80036	100	80008	300	280262	80108	200	80012	200	160028	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80010	300	640280	80110	200	80014	200	160024	1	80000	100
80204	40067	80101	101	80000	100	80008	300	640718	80108	200	80012	200	160024	1	80000	100
80204	40061	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80059	300	640918	80159	200	80072	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40589	80047	11	80036	10	80008	30	320190	0	80018	20	80012	0	20	160000	1	80000	10
80024	40050	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	640040	0	80010	20	80000	0	20	160000	1	80000	10

LDR (register, lsl, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations