Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDR (register, lsl, 64-bit)

Test 1: uops

Code:

  ldr x0, [x6, x7, lsl #3]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056901021110201000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000
10045451001110001000807610001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7, lsl #3]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570153401083010710001301301000318596146939514010630210100046022020008300031000030100
4020470050401033010310000301031000318596626940934010630212100046022420008300031000030100
4020470050401033010310000301031000318596626940934010630212100046022420008300031000030100
4020470051401033010310000301031000318596626940934010630212100046022420008300031000030100
4020470054401033010310000301031000318599056941924010630212100046022420008300031000030100
4020470050401033010310000301031000318596626940934010630212100046022420008300031000030100
4020470050401033010310000301031000318596626940934010630212100046029420034300091000030100
4020470076401033010310000301031000318596626940934010630212100046022420008300031000030100
4020470050401033010310000301031000318596626940934010630212100046022420008300031000030100
4020470050401033010310000301031000318596896941044010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0041

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570162400183001710001300401000318597046937284001630030100046004420008300041000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470114400133001310000300101000018598146947864001030020100006002020000300021000030010
4002470042400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldr x0, [x6, x7, lsl #3]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0050

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570160401083010710001301301000318596146939514010630210100046022020008300031000030100
4020570159401123011010002301351000318596896941064010630212100046022020008300021000030100
4020470041401023010210000301031000318594196940034010630212100046022420008300021000030100
4020470041401023010210000301031000318594196940034010630212100046022420008300021000030100
4020470041401023010210000301031000318594196940034010630212100046022420008300021000030100
4020470041401023010210000301031000318594196940034010630212100046022420008300021000030100
4020470041401023010210000301031000318594196940034010630212100046022420008300021000030100
4020470041401023010210000301031000318594196940034010630212100046022420008300021000030100
4020470041401023010210000301031001518621946951034015030251100176022420008300021000030100
4020470041401023010210000301031000318594196940034010630212100046022420008300021000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0043

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570149400183001710001300401001518616426944944006030069100176004020008300031000030010
4002470048400133001310000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470041400123001210000300101000018594906946544001030020100006002020000300021000030010
4002470043400123001210000300101000018595176946654001030020100006011420034300081000030010
4002470046400123001210000300101000318597796947784001630032100046002020000300021000030010
4002470043400123001210000300101000018595446946744001030020100006002020000300021000030010
4002470043400123001210000300101000018595446946744001030020100006002020000300021000030010
4002470043400123001210000300101000018595446946744001030020100006002020000300021000030010
4002470043400123001210000300101000018595446946744001030020100006002020000300021000030010

Test 4: throughput

Count: 8

Code:

  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  ldr x0, [x6, x7, lsl #3]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205405418013710180036100800083002802628010820080012200160028180000100
80204400578010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800103006402808011020080014200160024180000100
80204400678010110180000100800083006407188010820080012200160024180000100
80204400618010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800593006409188015920080072200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540589800471180036108000830320190080018208001202016000018000010
8002440050800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010
8002440043800111180000108000030640040080010208000002016000018000010