Icestorm: AUTIB measurements

Code:

  autib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	? int output thing (e9)	? int retires (ef)
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000
1004	6029	1001	1001	1000	52725	1000	1001	1000

Test 2: Latency 1->1

Code:

  autib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530425	10211	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100
10204	60029	10201	10201	10200	530325	10200	200	200	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529885	10031	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529885	10031	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010
10024	60029	10021	10021	10020	529785	10020	20	20	10011	10010

Test 3: Latency 1->2

Chain cycles: 1

Code:

  add x1, x0, x0
  mov x0, 0
  autib x0, x1

Initialization

  mov x0, 1

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
30204	70029	20201	20201	20202	1429543	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100
30204	70029	20201	20201	20202	1429568	20202	10204	20208	0	0	20101	0	0	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 6.0029

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	70029	20021	20021	20022	0	1429208	0	20022	10024	0	20028	20011	30010
30024	70029	20021	20021	20020	0	1429198	0	20020	10020	0	20020	20011	30010
30024	70029	20021	20021	20020	0	1429198	0	20020	10020	0	20020	20011	30010
30025	70059	20025	20025	20046	0	1429198	0	20020	10020	0	20020	20011	30010
30024	70029	20021	20021	20020	0	1429198	0	20020	10020	0	20020	20011	30010
30024	70029	20021	20021	20020	0	1429198	0	20020	10020	0	20060	20015	30010
30024	70029	20021	20021	20020	0	1429198	0	20020	10020	0	20028	20011	30010
30024	70029	20021	20021	20022	0	1429198	0	20020	10020	0	20020	20011	30010
30024	70029	20021	20021	20020	0	1429198	0	20020	10020	0	20020	20011	30010
30024	70029	20021	20021	20020	0	1429198	0	20020	10020	0	20020	20011	30010

Test 4: throughput

Count: 8

Code:

  autib x0, x8
  autib x1, x8
  autib x2, x8
  autib x3, x8
  autib x4, x8
  autib x5, x8
  autib x6, x8
  autib x7, x8

(requires arm64e binary, with arm64e_preview_abi boot arg)

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	160030	80201	80201	80202	1360379	80202	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360580	80220	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360533	80220	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	80101	0	0	80100
80204	160030	80201	80201	80202	1360481	80202	200	200	0	80101	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	160030	80021	80021	80022	1359941	80022	20	20	80011	80010
80025	160060	80029	80029	80039	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80025	160064	80031	80031	80040	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80021	80010
80024	160030	80021	80021	80020	1359931	80020	20	20	80011	80010

AUTIB

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations