Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ADDS (sxtx, 64-bit)

Test 1: uops

Code:

  adds x0, x0, x1, sxtx
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000
100410301001100110002504310001000200010011000

Test 2: Latency 1->2

Code:

  adds x0, x0, x1, sxtx
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101082516411010610206202201000110100
10204100301010110101101082517741010810208202201000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282531291003010030200201001110010
10025100601003510035100682532561002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200401001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010

Test 3: Latency 1->3

Code:

  adds x0, x1, x0, sxtx
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204100301010110101101092516581010610206202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10205100601011710117101482517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100
10204100301010110101101082517741010810208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024100301002110021100282531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10025100601003510035100702531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010
10024100301002110021100202531611002010020200201001110010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  adds x0, x1, x2, sxtx
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302010120101201075192842010820216302212000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302001120011200185194542001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010
20024200302001120011200105195982001020020300202000120010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  adds x0, x1, x2, sxtx
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302010120101201075194352010720212302242000120100
20204200302010120101201085194342010720214302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100
20204200302010120101201085195482010820216302242000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302001120011002001805195072001720032300202000120010
20024200302001120011002001005195982001020020300202000120010
20024200302001120011002001005195982001020020300202000120010
20024200302001120011002001005195982001020020300202000120010
20024200302001120011002001005195982001020020300202000120010
20024200302001120011002001005195982001020020300412000120010
4359771326442893577165845335820615195072001720032300202000120010
20024200302001120011002001005195982001020020300202000120010
20024200302001120011002001005195982001020020300202000120010
20025200602002520025002005905194762001020020300202000120010

Test 6: throughput

Count: 8

Code:

  adds x0, x8, x9, sxtx
  adds x1, x8, x9, sxtx
  adds x2, x8, x9, sxtx
  adds x3, x8, x9, sxtx
  adds x4, x8, x9, sxtx
  adds x5, x8, x9, sxtx
  adds x6, x8, x9, sxtx
  adds x7, x8, x9, sxtx
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
802044008780111801118011424044380148802481602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100
802044008180112801128011524034580115802161602328001280100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800244006980034800348003724021480068800691600528002280010
800244003680021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010
800244003080021800218002024006580020800201600208001180010