Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

ANDS (register, asr, 64-bit)

Test 1: uops

Code:

  ands x0, x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000

Test 2: Latency 1->2

Code:

  ands x0, x0, x1, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290011010410206202122000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010

Test 3: Latency 1->3

Code:

  ands x0, x1, x0, asr #17
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290871010410208202122000110100
10204200302010120101101045290871010410208202122000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200772012220122101395290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255291921002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  ands x0, x1, x2, asr #17
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201060789233020105202120302183000120100
20204300303010130101201050789310020105202100302183000120100
20204300303010130101201050789369020105202120302183000120100
20204300303010130101201050789369020105202120302183000120100
20204300303010130101201050789738020143202600302183000120100
20204300303010130101201050789369020105202120302183000120100
20204300303010130101201050789369020105202120302183000120100
20204300303010130101201050789369020105202120302183000120100
202043003030101301012010524791462680202062034424302183000120100
20204300303010130101201050789369020105202120302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20025300603002530025200517894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  ands x0, x1, x2, asr #17
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201057893112010520212302183000120100
20204300303010130101201077893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20205300603011530115201407893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157893462001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300813001520010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107913882016220186300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 6: throughput

Count: 8

Code:

  ands x0, x8, x9, asr #17
  ands x1, x8, x9, asr #17
  ands x2, x8, x9, asr #17
  ands x3, x8, x9, asr #17
  ands x4, x8, x9, asr #17
  ands x5, x8, x9, asr #17
  ands x6, x8, x9, asr #17
  ands x7, x8, x9, asr #17
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8020453430160118160118801241099808801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416032816006580100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002453399160045160045800501107836800488004816002016001180010
8002553411160087160087800881104624800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010