Icestorm: LDRSB (post-index, 64-bit) measurements

Code:

  ldrsb x0, [x6], #8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1227	2040	1021	1019	1042	1000	20954	17645	2000	1000	1000	1000	1000	1001	1000	1000
2004	1079	2001	1001	1000	1000	1000	20845	18034	2000	1000	1000	1000	1000	1001	1000	1000
2004	1083	2001	1001	1000	1000	1000	20945	17627	2000	1000	1000	1000	1000	1001	1000	1000
2004	1084	2001	1001	1000	1000	1000	21133	17700	2000	1000	1000	1000	1000	1001	1000	1000
2004	1108	2001	1001	1000	1000	1000	20927	17880	2000	1000	1000	1000	1000	1001	1000	1000
2004	1122	2001	1001	1000	1000	1000	21298	17890	2000	1000	1000	1000	1000	1001	1000	1000
2004	1084	2001	1001	1000	1000	1000	20276	18572	2000	1000	1000	1000	1000	1001	1000	1000
2004	1068	2001	1001	1000	1000	1000	21222	17828	2000	1000	1000	1000	1000	1001	1000	1000
2004	1067	2001	1001	1000	1000	1000	21053	17609	2000	1000	1000	1000	1000	1001	1000	1000
2004	1067	2001	1001	1000	1000	1000	20779	18015	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb x0, [x6], #8
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0119

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50209	71246	50159	40154	10005	40247	10002	1850506	534722	50108	40211	10003	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534840	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534840	50109	40212	10004	70289	10013	40015	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534840	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534840	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850604	534824	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534840	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534840	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850658	534840	50109	40212	10004	70221	10004	40004	10000	40100
50204	70117	50104	40104	10000	40106	10003	1850604	534824	50109	40212	10004	70221	10004	40004	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0147

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71218	50070	40065	10005	40156	10003	1850748	535202	50019	40032	10004	70020	10000	40004	10000	40010
50024	70119	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850552	535121	50010	40020	10000	70112	10014	40015	10000	40010
50024	70115	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	40010
50024	70113	50014	40014	10000	40010	10000	1850606	535137	50010	40020	10000	70020	10000	40004	10000	40010
50025	70268	50027	40025	10002	40049	10000	1851038	535274	50010	40020	10000	70109	10013	40016	10000	40010
50024	70137	50014	40014	10000	40010	10000	1851497	535416	50010	40020	10000	70020	10000	40004	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsb x0, [x6], #8
  ldrsb x0, [x7], #8
  ldrsb x0, [x8], #8
  ldrsb x0, [x9], #8
  ldrsb x0, [x10], #8
  ldrsb x0, [x11], #8
  ldrsb x0, [x12], #8
  ldrsb x0, [x13], #8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44197	160416	80313	80103	80316	80011	240610	641903	160123	80212	80012	80212	80012	80009	80000	80100
160204	43234	160109	80109	80000	80112	80010	240523	645228	160120	80210	80010	80212	80012	80009	80000	80100
160204	43224	160109	80109	80000	80112	80012	240529	640722	160124	80212	80012	80210	80010	80007	80000	80100
160204	43227	160109	80109	80000	80112	80011	240529	643122	160123	80212	80012	80212	80012	80009	80000	80100
160204	43223	160109	80109	80000	80112	80009	240529	644495	160121	80212	80012	80254	80054	80051	80000	80100
160204	43231	160109	80109	80000	80112	80011	240529	638970	160123	80212	80012	80254	80054	80051	80000	80100
160204	43232	160109	80109	80000	80112	80011	240529	645335	160123	80212	80012	80212	80012	80009	80000	80100
160204	43222	160107	80107	80000	80108	80010	240529	641542	160122	80212	80012	80212	80012	80009	80000	80100
160204	43223	160109	80109	80000	80112	80012	241159	632441	160124	80212	80012	80212	80012	80009	80000	80100
160204	43265	160109	80109	80000	80112	80008	240920	641888	160120	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5402

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44297	160320	80220	80100	80221	80011	240308	640864	160033	80032	80012	80020	80000	80001	80000	80010
160024	43222	160011	80011	80000	80010	80000	240179	646008	160010	80020	80000	80020	80000	80001	80000	80010
160024	43217	160011	80011	80000	80010	80000	240179	642643	160010	80020	80000	80020	80000	80001	80000	80010
160024	43217	160011	80011	80000	80010	80000	240179	639235	160010	80020	80000	80020	80000	80001	80000	80010
160024	43219	160011	80011	80000	80010	80000	240179	642793	160010	80020	80000	80020	80000	80001	80000	80010
160024	43215	160011	80011	80000	80010	80000	240179	644745	160010	80020	80000	80020	80000	80001	80000	80010
160024	43217	160011	80011	80000	80010	80000	240179	645248	160010	80020	80000	80020	80000	80001	80000	80010
160024	43217	160011	80011	80000	80010	80000	240179	639235	160010	80020	80000	80020	80000	80001	80000	80010
160024	43217	160011	80011	80000	80010	80000	240179	644041	160010	80020	80000	80020	80000	80001	80000	80010
160024	43217	160011	80011	80000	80010	80000	240179	636486	160010	80020	80000	80020	80000	80001	80000	80010

LDRSB (post-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations