Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PSTL1KEEP)

Test 1: uops

Code:

  prfm pstl1keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2093	1001	1	1000	1000	34900	1000	1000	1000	1	1000
1004	2104	1001	1	1000	1000	34930	1000	1000	1000	1	1000
1004	2076	1001	1	1000	1000	34816	1000	1000	1000	1	1000
1004	2096	1001	1	1000	1000	34928	1000	1000	1000	1	1000
1004	2101	1001	1	1000	1000	34928	1000	1000	1000	1	1000
1004	2076	1001	1	1000	1000	34922	1000	1000	1000	1	1000
1004	2104	1001	1	1000	1000	34684	1000	1000	1000	1	1000
1004	2087	1001	1	1000	1000	34976	1000	1000	1000	1	1000
1004	2080	1001	1	1000	1000	34618	1000	1000	1000	1	1000
1004	2097	1001	1	1000	1000	34668	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pstl1keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.9976

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20610	20105	10105	10000	10111	10002	61634	348925	20109	10209	10009	10207	10007	10003	10000	10100
20204	20100	20101	10101	10000	10101	10000	61540	346633	20100	10202	10002	10204	10004	10003	10000	10100
20204	20130	20101	10101	10000	10100	10000	61453	346647	20102	10204	10004	10202	10002	10001	10000	10100
20204	19968	20101	10101	10000	10100	10002	61483	349169	20110	10210	10010	10204	10004	10003	10000	10100
20204	20066	20105	10105	10000	10106	10000	61521	348769	20106	10208	10008	10210	10010	10003	10000	10100
20204	19970	20104	10104	10000	10103	10000	61526	348453	20102	10204	10004	10210	10010	10005	10000	10100
20204	19922	20102	10102	10000	10104	10000	61641	347663	20106	10208	10008	10204	10004	10001	10000	10100
20204	19985	20101	10101	10000	10100	10002	61496	349125	20110	10210	10010	10206	10006	10002	10000	10100
20204	19892	20106	10106	10000	10112	10000	61744	346941	20104	10206	10006	10204	10004	10001	10000	10100
20204	20117	20102	10102	10000	10106	10000	61717	345953	20102	10204	10004	10202	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0176

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	24381	20012	10012	10000	10015	10000	60906	349463	20015	10027	10007	10020	10000	10001	10000	10010
20024	20107	20011	10011	10000	10010	10000	60496	345513	20010	10020	10000	10020	10000	10001	10000	10010
20024	20124	20011	10011	10000	10010	10000	61166	348553	20010	10020	10000	10020	10000	10001	10000	10010
20024	20075	20011	10011	10000	10010	10000	61107	349567	20010	10020	10000	10020	10000	10001	10000	10010
20024	20065	20011	10011	10000	10010	10000	60999	349629	20010	10020	10000	10020	10000	10001	10000	10010
20024	19995	20011	10011	10000	10010	10000	60857	347991	20010	10020	10000	10020	10000	10001	10000	10010
20024	20150	20011	10011	10000	10010	10000	61153	350243	20010	10020	10000	10020	10000	10001	10000	10010
20024	20149	20011	10011	10000	10010	10000	61181	349909	20010	10020	10000	10020	10000	10001	10000	10010
20024	20048	20011	10011	10000	10010	10000	60544	349045	20010	10020	10000	10020	10000	10001	10000	10010
20024	20077	20011	10011	10000	10010	10000	61029	350785	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pstl1keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.9387

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	19479	10101	101	10000	100	10000	300	339178	10100	200	10004	200	10008	1	10000	100
10204	19247	10101	101	10000	100	10000	300	333056	10100	200	10004	200	10004	1	10000	100
10204	19207	10101	101	10000	100	10000	300	335544	10100	200	10004	200	10004	1	10000	100
10204	19244	10101	101	10000	100	10002	300	335382	10102	200	10012	200	10004	1	10000	100
10204	19367	10101	101	10000	100	10004	300	337914	10104	200	10012	200	10008	1	10000	100
10204	19226	10101	101	10000	100	10000	300	332656	10100	200	10008	200	10069	1	10000	100
10204	19375	10101	101	10000	100	10000	300	334828	10100	200	10008	200	10012	1	10000	100
10204	19420	10101	101	10000	100	10002	300	336588	10102	200	10012	200	10004	1	10000	100
10204	19144	10101	101	10000	100	10002	300	337332	10102	200	10012	200	10008	1	10000	100
10204	19373	10101	101	10000	100	10000	300	339204	10100	200	10008	200	10008	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.8718

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	20065	10011	11	10000	10	10000	30	349282	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10
10024	20048	10011	11	10000	10	10000	30	349214	10010	20	10000	20	10000	1	10000	10