Icestorm: LDRB (register, sxtw) measurements

Code:

  ldrb w0, [x6, w7, sxtw]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	679	1021	1	1020	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	550	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000
1004	543	1001	1	1000	1000	8040	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70156	40108	30107	10001	30130	10015	1860418	694256	40150	30249	10017	60220	20008	30003	10000	30100
40204	70053	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859980	694200	40150	30251	10017	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70263	40018	30017	10001	30040	10000	1859658	693674	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10012	1861561	730314	40054	30059	10013	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010
40025	70084	40021	30019	10002	30045	10000	1862433	695852	40010	30020	10000	60020	20000	30002	10000	30010
40024	70049	40013	30013	10000	30013	10003	1859488	693646	40016	30030	10004	60120	20036	30009	10000	30010
40024	70073	40012	30012	10000	30010	10000	1859598	694697	40010	30020	10000	60020	20000	30002	10000	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrb w0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70169	40108	30107	10001	30130	10003	1859296	693806	40106	30210	10004	60220	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859419	694003	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70041	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10015	1859737	694074	40150	30247	10017	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100
40204	70040	40102	30102	10000	30103	10003	1859392	693993	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
40025	70150	40018	30017	10001	30040	10000	1859658	693674	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40025	70072	40020	30018	10002	30045	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70045	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010
40024	70042	40012	30012	10000	30010	10000	1859517	694664	40010	30020	10000	60020	20000	30002	10000	0	30010

Test 4: throughput

Count: 8

Code:

  ldrb w0, [x6, w7, sxtw]
  ldrb w0, [x6, w7, sxtw]
  ldrb w0, [x6, w7, sxtw]
  ldrb w0, [x6, w7, sxtw]
  ldrb w0, [x6, w7, sxtw]
  ldrb w0, [x6, w7, sxtw]
  ldrb w0, [x6, w7, sxtw]
  ldrb w0, [x6, w7, sxtw]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40164	80133	101	80032	100	80008	300	256262	80108	200	80012	200	160024	1	80000	100
80204	40057	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160028	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160138	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640268	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40441	80039	11	80028	10	80136	639	636591	80245	215	80155	20	160000	1	80000	10
80024	40062	80011	11	80000	10	80000	30	640544	80010	20	80000	20	160000	1	80000	10
80024	40054	80011	11	80000	10	80000	30	642056	80010	20	80000	20	160000	1	80000	10
80024	40542	80131	11	80120	10	80000	30	640202	80010	20	80000	20	160000	1	80000	10
80024	40061	80011	11	80000	10	80000	30	640220	80010	20	80000	20	160114	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160228	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40289	80071	11	80060	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10
80024	40172	80041	11	80030	10	80000	30	640238	80010	20	80000	20	160114	1	80000	10
80024	40054	80011	11	80000	10	80000	30	640238	80010	20	80000	20	160000	1	80000	10

LDRB (register, sxtw)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations