Icestorm: SUBS (sxtb, 32-bit) measurements

Code:

  subs w0, w0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Code:

  subs w0, w0, w1, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529044	10104	10206	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529215	10025	10030	20044	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010

Test 3: Latency 1->3

Code:

  subs w0, w1, w0, sxtb

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529044	10104	10206	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529420	10139	10248	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10205	20060	20117	20117	10139	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs w0, w1, w2, sxtb
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20105	789209	20106	20214	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789151	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20205	30060	30115	30115	20141	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	20015	789401	20015	20032	30020	30001	20010
20025	30060	30025	30025	20051	789380	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789790	20051	20072	30104	30015	20010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs w0, w1, w2, sxtb
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20106	789071	20106	20214	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789714	20141	20256	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	20015	789401	20015	20032	30038	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010

Test 6: throughput

Count: 8

Code:

  subs w0, w8, w9, sxtb
  subs w1, w8, w9, sxtb
  subs w2, w8, w9, sxtb
  subs w3, w8, w9, sxtb
  subs w4, w8, w9, sxtb
  subs w5, w8, w9, sxtb
  subs w6, w8, w9, sxtb
  subs w7, w8, w9, sxtb

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53404	160114	160114	80123	0	1099833	0	80127	80228	0	160248	160014	80100
80204	53417	160114	160114	80123	0	1100076	0	80123	80224	0	160328	160065	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100
80204	53404	160114	160114	80123	0	1100076	0	80123	80224	0	160248	160014	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53417	160042	160042	80048	0	1107842	0	80048	80048	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010
80024	53371	160021	160021	80020	0	1107732	0	80020	80020	0	160020	160011	80010

SUBS (sxtb, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations