Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDURSH (64-bit)

Test 1: uops

Code:

  ldursh x0, [x6, #1]
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056551025110241000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000
10045431001110001000804010001000100011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldursh x0, [x6, #1]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570147401083010710001301301000318594856939734010630212100046022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100
4020470047401033010310000301031001518601156942564015030247100176022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100
4020470047401033010310000301031000318595816940634010630212100046022410004300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570156400183001710001300401000018597066947344001030020100006002010000300031000030010
4002470049400133001310000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006011410017300081000030010
4002470049400133001310000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010
4002470042400123001210000300101000018595176946644001030020100006002010000300021000030010

Test 3: throughput

Count: 8

Code:

  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  ldursh x0, [x6, #1]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
80205401728012910180028100800083002801908010820080012200800121800000100
80204400528010110180000100800083006400708010820080012200800121800000100
80204401378010110180000100800083006401248010820080012200800121800000100
80204400498010110180000100800083006401428010820080012200800121800000100
80204400618010110180000100800083004451588010820080012200800121800000100
80204400558010510180004100800083003361368010820080012200800121800000100
80204400498010110180000100800083006402688010820080012200800121800000100
80204400498010110180000100800083006401428010820080012200800121800000100
80204400498010110180000100800083006401428010820080012200800121800000100
80204400498010110180000100800083006401428010820080012200800121800000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540260800371180026108000830640268800182080012208000018000010
8002440054800111180000108000030640238800102080000208000018000010
8002440054800111180000108000030640238800102080000208000018000010
8002440054800111180000108000030640238800102080000208000018000010
8002540379800411180030108000030640238800102080000208000018000010
8002440054800111180000108000030640238800102080000208000018000010
8002440054800111180000108000030640238800102080000208000018000010
8002440054800111180000108000030640238800102080000208000018000010
8002440054800111180000108000030640238800102080000208000018000010
8002440060800111180000108000030640238800102080000208000018000010