Icestorm: STUR (32-bit) measurements

Code:

  stur w0, [x6, #1]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1149	1019	1	1018	1000	17007	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17025	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17079	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17025	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	2000	1	1000
1004	1045	1001	1	1000	1000	17007	1000	1000	2000	1	1000

Count: 8

Code:

  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]
  stur w0, [x6, #1]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80150	80119	101	80018	100	80001	300	1359974	80101	200	80008	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80034	300	1360147	80134	200	80049	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160016	1	80000	100
80204	80054	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160016	1	80000	100
80204	80047	80101	101	80000	100	80001	300	1360046	80101	200	80008	200	160104	1	80000	100
80204	80047	80101	101	80000	100	80037	300	1360258	80137	200	80052	200	160016	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80026	80181	80046	11	80035	10	80001	30	1359868	0	80011	20	80008	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80025	80065	80028	11	80017	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10
80024	80037	80011	11	80000	10	80000	30	1359847	0	80010	20	80000	0	20	160000	1	80000	10

STUR (32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations