Icestorm: UDIV (medium, 64-bit) measurements

Code:

  udiv x0, x1, x2

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000
1004	13030	2001	2001	1000	115532	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x1, x1, x0
  eor x1, x1, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	150030	40201	40201	30203	4018372	30230	30246	60220	40101	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	40101	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	40101	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60294	40104	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	40101	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	40101	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	40101	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60296	40104	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	40101	30100
30204	150030	40201	40201	30203	4018070	30203	30212	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	150030	40011	40011	30013	0	4018298	0	30010	30020	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	30010	30020	0	60020	40001	30010
30025	150060	40014	40014	30040	0	4018298	0	30010	30020	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	30010	30020	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	30010	30020	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	30010	30020	0	60020	40001	30010
30025	150060	40014	40014	30042	0	4018329	0	30010	30020	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	30010	30020	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	30010	30020	0	60020	40001	30010
30024	150030	40011	40011	30010	0	4018329	0	30010	30020	0	60020	40001	30010

Test 3: Latency 1->3

Chain cycles: 2

Code:

  udiv x0, x1, x2
  eor x2, x2, x0
  eor x2, x2, x0

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30204	150030	40201	40201	0	0	30203	0	0	4018042	0	0	30203	30210	0	0	60224	40101	30100
30204	150030	40201	40201	0	0	30203	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100
30204	150030	40201	40201	0	0	30203	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100
30205	150060	40204	40204	0	0	30230	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100
30204	150030	40201	40201	0	0	30203	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100
30204	150030	40201	40201	0	0	30203	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100
30204	150030	40201	40201	0	0	30203	0	0	4018070	0	0	30203	30212	0	0	60298	40104	30100
30205	150060	40206	40206	0	0	30232	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100
30204	150030	40201	40201	0	0	30203	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100
30204	150030	40201	40201	0	0	30203	0	0	4018070	0	0	30203	30212	0	0	60224	40101	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 2 chain cycles): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
30024	150030	40011	40011	0	0	30013	0	4018648	30042	30066	60040	40001	30010
30024	150030	40011	40011	0	0	30010	0	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	0	0	30010	0	4018329	30010	30020	60116	40004	30010
30024	150030	40011	40011	0	0	30010	0	4018329	30010	30020	60020	40001	30010
34821	171129	44096	42487	51	1558	32343	41	4018298	30010	30020	60020	40001	30010
30024	150030	40011	40011	0	0	30010	0	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	0	0	30010	0	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	0	0	30010	0	4018329	30010	30020	60020	40001	30010
30025	150060	40014	40014	0	0	30041	0	4018329	30010	30020	60020	40001	30010
30024	150030	40011	40011	0	0	30010	0	4018329	30010	30020	60020	40001	30010

Test 4: throughput

Code:

  udiv x0, x1, x2

Initialization

  mov x1, #0xffffffff
  mov x2, #3

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10206	130090	20107	20107	10118	0	1159832	0	0	10100	10206	0	0	20216	20001	10100
10204	130030	20101	20101	10100	0	1159832	0	0	10100	10206	0	0	20216	20001	10100
10204	130030	20101	20101	10100	0	1159832	0	0	10100	10208	0	0	20216	20001	10100
10204	130030	20101	20101	10100	0	1159832	0	0	10100	10208	0	0	20216	20001	10100
10204	130030	20101	20101	10100	0	1159948	0	0	10109	10224	0	0	20216	20001	10100
10204	130030	20101	20101	10100	0	1159832	0	0	10100	10208	0	0	20216	20001	10100
10205	130060	20104	20104	10109	0	1159948	0	0	10109	10223	0	0	20216	20001	10100
10205	130060	20104	20104	10109	0	1160064	0	0	10118	10240	0	0	20248	20004	10100
10204	130030	20101	20101	10100	0	1159832	0	0	10100	10208	0	0	20216	20001	10100
10204	130030	20101	20101	10100	0	1159832	0	0	10100	10208	0	0	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 13.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	130030	20021	20021	10020	0	1159592	0	10020	10026	0	20070	20014	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20020	20011	10010
10024	130030	20021	20021	10020	0	1159708	0	10029	10044	0	20020	20011	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20020	20011	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20020	20011	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20068	20014	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20068	20014	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20062	20014	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20020	20011	10010
10024	130030	20021	20021	10020	0	1159592	0	10020	10020	0	20020	20011	10010

UDIV (medium, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations