Icestorm: CMP (register, 32-bit) measurements

Code:

  cmp w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	504	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	392	1001	1001	1000	3000	1000	1000	2000	1001
1004	389	1001	1001	1000	3000	1000	1000	2000	1001
1004	396	1001	1001	1000	3000	1000	1000	2000	1001
1004	389	1001	1001	1000	3000	1000	1000	2000	1001
1004	391	1001	1001	1000	3000	1000	1000	2000	1001
1004	394	1001	1001	1000	3000	1000	1000	2000	1001
1004	393	1001	1001	1000	3000	1000	1000	2000	1001
1004	390	1001	1001	1000	3000	1000	1000	2000	1001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp w0, w1
  cset x0, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519338	20108	20214	30221	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519476	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30111	20015	10010
20025	20060	20025	20025	20059	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20019	519516	20018	20034	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp w0, w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	0	519464	0	0	20110	20218	0	0	30221	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30291	20023	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30224	20001	10100
20204	20030	20101	20101	20108	0	520010	0	0	20151	20259	0	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30224	20001	10100
20204	20030	20101	20101	20108	0	519548	0	0	20108	20216	0	0	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519476	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 4: throughput

Count: 8

Code:

  cmp w0, w1
  cmp w0, w1
  cmp w0, w1
  cmp w0, w1
  cmp w0, w1
  cmp w0, w1
  cmp w0, w1
  cmp w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3635

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	29154	80115	80115	80119	4992	390801	55988	719	94918	92974	5918	51	160236	80013	100
80204	29132	80114	80114	80119	0	240354	0	0	80118	80220	0	0	160240	80012	100
80204	29082	80113	80113	80118	0	240351	0	0	80117	80218	0	0	160240	80015	100
80204	29066	80113	80113	80118	0	240354	0	0	80118	80220	0	0	160312	80052	100
80204	29080	80114	80114	80119	0	240357	0	0	80119	80220	0	0	160240	80015	100
80204	29120	80113	80113	80118	0	240351	0	0	80117	80220	0	0	160240	80013	100
80204	29082	80115	80115	80119	0	240357	0	0	80119	80220	0	0	160240	80015	100
80204	29082	80113	80113	80118	0	240354	0	0	80118	80220	0	0	160240	80012	100
80204	29082	80115	80115	80119	0	240354	0	0	80118	80220	0	0	160240	80015	100
80204	29087	80115	80115	80119	0	240354	0	0	80118	80220	0	0	160240	80015	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3631

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	30519	80034	80034	80038	240101	80020	80020	160020	80011	10
80024	29156	80021	80021	80020	240114	80020	80020	160020	80011	10
80024	29155	80021	80021	80020	240112	80020	80020	160020	80011	10
80024	29102	80021	80021	80020	240115	80020	80020	160020	80011	10
80024	29129	80021	80021	80020	240112	80020	80020	160020	80011	10
80024	29129	80021	80021	80020	240096	80020	80020	160020	80011	10
80024	29113	80021	80021	80020	240096	80020	80020	160020	80011	10
80024	29155	80021	80021	80020	240112	80020	80020	160020	80011	10
80024	29103	80021	80021	80020	240103	80020	80020	160020	80011	10
80024	29122	80021	80021	80020	240103	80020	80020	160020	80011	10

CMP (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations