Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLIL3KEEP)

Test 1: uops

Code:

  prfm plil3keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2129	1001	1	1000	1000	35878	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2120	1001	1	1000	1000	35244	1000	1000	1000	1	1000
1004	2096	1001	1	1000	1000	34998	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm plil3keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.9994

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20565	20102	10102	10000	10101	10000	61357	351907	20103	10205	10005	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100
20204	20196	20105	10105	10000	10104	10000	61276	351907	20104	10206	10006	10206	10006	10005	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0067

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	23267	20014	10014	10000	10019	10008	61211	349625	20031	10033	10014	10020	10000	10001	10000	10010
20024	20067	20011	10011	10000	10010	10000	61039	349535	20010	10020	10000	10020	10000	10001	10000	10010
20024	20067	20011	10011	10000	10010	10000	61039	349535	20010	10020	10000	10020	10000	10001	10000	10010
20024	20067	20011	10011	10000	10010	10000	61039	349535	20010	10020	10000	10020	10000	10001	10000	10010
20024	20160	20011	10011	10000	10010	10000	61164	348645	20010	10020	10000	10020	10000	10001	10000	10010
20024	20054	20011	10011	10000	10010	10000	61061	349955	20010	10020	10000	10020	10000	10001	10000	10010
20024	20068	20011	10011	10000	10010	10000	60940	351605	20010	10020	10000	10020	10000	10001	10000	10010
20024	20067	20011	10011	10000	10010	10000	61039	349535	20010	10020	10000	10020	10000	10001	10000	10010
20024	20067	20011	10011	10000	10010	10000	61039	349535	20010	10020	10000	10020	10000	10001	10000	10010
20024	20067	20011	10011	10000	10010	10000	61039	349535	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm plil3keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20422	10101	101	10000	100	10000	300	357272	10100	200	10006	200	10012	1	10000	100
10204	20764	10101	101	10000	100	10000	300	359660	10100	200	10008	200	10071	1	10000	100
10204	20485	10101	101	10000	100	10002	300	356174	10102	200	10010	200	10012	1	10000	100
10204	20418	10101	101	10000	100	10000	300	357140	10100	200	10008	200	10008	1	10000	100
10204	20381	10101	101	10000	100	10004	300	354798	10104	200	10012	200	10012	1	10000	100
10204	20493	10101	101	10000	100	10000	300	357212	10100	200	10008	200	10012	1	10000	100
10204	20498	10101	101	10000	100	10000	300	357370	10100	200	10008	200	10004	1	10000	100
10204	20520	10101	101	10000	100	10000	300	357506	10100	200	10004	200	10004	1	10000	100
10204	20485	10101	101	10000	100	10006	300	355834	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0905

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	19554	10011	11	10000	10	10000	30	334668	10010	20	10004	22	10234	2	10000	10
10024	19285	10011	11	10000	10	10000	30	337062	10010	20	10004	20	10004	1	10000	10
10024	18883	10011	11	10000	10	10000	30	331122	10010	20	10000	20	10000	1	10000	10
10024	18725	10011	11	10000	10	10000	30	333646	10010	20	10000	20	10000	1	10000	10
10024	18726	10011	11	10000	10	10000	30	334598	10010	20	10000	20	10000	1	10000	10
10024	19490	10011	11	10000	10	10000	30	339568	10010	20	10000	20	10000	1	10000	10
10024	18734	10011	11	10000	10	10000	30	336398	10010	20	10000	20	10000	1	10000	10
10024	19445	10011	11	10000	10	10000	30	332468	10010	20	10000	20	10000	1	10000	10
10024	19253	10011	11	10000	10	10000	30	337632	10010	20	10000	20	10000	1	10000	10
10024	19009	10011	11	10000	10	10000	30	338418	10010	20	10000	20	10000	1	10000	10