Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CMP (sxtb, 32-bit)

Test 1: uops

Code:

  cmp w0, w1, sxtb
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001
1004698200120011000146781000100020002001

Test 2: Latency 3->1

Chain cycles: 1

Code:

  cmp w0, w1, sxtb
  cset x0, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201067892312010520210302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024302243009530095201687893802001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010
20024300303001130011200107894382001020020300203000110010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  cmp w0, w1, sxtb
  cset x1, cc
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201067893692010520212302213000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100
20204300303010130101201057893692010520212302183000110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
2002430030300113001120015789381200152003030020030001010010
2002530060300253002520050789379200102002030020030001010010
2002430030300113001120010789438200102002030020030001010010
2002430030300113001120010789197200152003030035030001010010
2002430030300113001120015789459200152003230038030001010010
2002430030300113001120015789459200152003230038030001010010
2002430030300113001120015789459200152003230038030001010010
2002430030300113001120015789459200152003230038030001010010
2002530060300253002520050789459200152003230098030015010010
2002430030300113001120010789438200102002030020030001010010

Test 4: throughput

Count: 8

Code:

  cmp w0, w1, sxtb
  cmp w0, w1, sxtb
  cmp w0, w1, sxtb
  cmp w0, w1, sxtb
  cmp w0, w1, sxtb
  cmp w0, w1, sxtb
  cmp w0, w1, sxtb
  cmp w0, w1, sxtb
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
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80205534351601621601628016311776358012380224160248016001400100
80204534021601141601148012311776078012380224160248016001400100
80204534021601141601148012311776278012380224160248016001400100
80204534021601141601148012311776038012380224160248016001400100
80204534021601141601148012311776318012380224160248016001400100
80204534021601141601148012311775978012380224160248016001400100
80204534021601141601148012311776278012380224160248016001400100
80204534021601141601148012311778448016680268160248016001400100
80204534021601141601148012311775998012380224160248016001400100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002453403160039160039800471170032800208002016002016001110
8002453371160021160021800201170032800208002016002016001110
8002453371160021160021800201170026800208002016002016001110
8002453371160021160021800201170032800208002016002016001110
8002453371160021160021800201170032800208002016002016001110
8002453371160021160021800201170032800208002016002016001110
8002453371160021160021800201170032800208002016014816007410
8002453371160021160021800201170032800208002016002016001110
8002453371160021160021800201170032800208002016002016001110
8002453371160021160021800201170032800208002016002016001110