Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
cmp w0, w1, sxtb
mov x0, 1 mov x1, 2
(no loop instructions)
Retires: 1.000
Issues: 2.000
Integer unit issues: 2.001
Load/store unit issues: 0.000
SIMD/FP unit issues: 0.000
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
1004 | 698 | 2001 | 2001 | 1000 | 14678 | 1000 | 1000 | 2000 | 2001 |
Chain cycles: 1
Code:
cmp w0, w1, sxtb cset x0, cc
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20204 | 30030 | 30101 | 30101 | 20106 | 789231 | 20105 | 20210 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20024 | 30224 | 30095 | 30095 | 20168 | 789380 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 30001 | 10010 |
Chain cycles: 1
Code:
cmp w0, w1, sxtb cset x1, cc
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
20204 | 30030 | 30101 | 30101 | 20106 | 789369 | 20105 | 20212 | 30221 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
20204 | 30030 | 30101 | 30101 | 20105 | 789369 | 20105 | 20212 | 30218 | 30001 | 10100 |
Result (median cycles for code, minus 1 chain cycle): 2.0030
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
20024 | 30030 | 30011 | 30011 | 20015 | 789381 | 20015 | 20030 | 30020 | 0 | 30001 | 0 | 10010 |
20025 | 30060 | 30025 | 30025 | 20050 | 789379 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789197 | 20015 | 20030 | 30035 | 0 | 30001 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20015 | 789459 | 20015 | 20032 | 30038 | 0 | 30001 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20015 | 789459 | 20015 | 20032 | 30038 | 0 | 30001 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20015 | 789459 | 20015 | 20032 | 30038 | 0 | 30001 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20015 | 789459 | 20015 | 20032 | 30038 | 0 | 30001 | 0 | 10010 |
20025 | 30060 | 30025 | 30025 | 20050 | 789459 | 20015 | 20032 | 30098 | 0 | 30015 | 0 | 10010 |
20024 | 30030 | 30011 | 30011 | 20010 | 789438 | 20010 | 20020 | 30020 | 0 | 30001 | 0 | 10010 |
Count: 8
Code:
cmp w0, w1, sxtb cmp w0, w1, sxtb cmp w0, w1, sxtb cmp w0, w1, sxtb cmp w0, w1, sxtb cmp w0, w1, sxtb cmp w0, w1, sxtb cmp w0, w1, sxtb
mov x0, 1 mov x1, 2
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 0.6675
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
80204 | 53427 | 160118 | 160118 | 80126 | 1177761 | 80130 | 80230 | 160252 | 0 | 160016 | 0 | 0 | 100 |
80205 | 53435 | 160162 | 160162 | 80163 | 1177635 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177607 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177627 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177603 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177631 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177597 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177627 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177844 | 80166 | 80268 | 160248 | 0 | 160014 | 0 | 0 | 100 |
80204 | 53402 | 160114 | 160114 | 80123 | 1177599 | 80123 | 80224 | 160248 | 0 | 160014 | 0 | 0 | 100 |
Result (median cycles for code divided by count): 0.6671
retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | dispatch int uop (56) | int uops in schedulers (59) | dispatch uop (78) | map int uop (7c) | map int uop inputs (7f) | ? int output thing (e9) | ? int retires (ef) |
80024 | 53403 | 160039 | 160039 | 80047 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170026 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160148 | 160074 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |
80024 | 53371 | 160021 | 160021 | 80020 | 1170032 | 80020 | 80020 | 160020 | 160011 | 10 |