Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSW (register, sxtw)

Test 1: uops

Code:

  ldrsw x0, [x6, w7, sxtw]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056901027110261000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045541001110001000825610001000200011000
10045541001110001000823810001000200011000
10045541001110001000823810001000200011000
10045501001110001000816610001000200011000
10045551001110001000816610001000200011000
10045501001110001000816610001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570155401083010710001301301000318594856938764010630210100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031001518601966942504015030247100176022420008300031000030100
4020470048401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470051401033010310000301031000418603917289064010730212100056022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570173400193001810001300401000318597256947584001630032100046002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002570091400223002010002300451000018605166950644001030020100006002020000300031000030010
4002470049400133001310000300101000018598146947784001030020100006002020000300031000030010
4002570112400213001910002300451000318601697008084001630032100046002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, sxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
402057015540108301071000130130100031859350693826401063021010004602202000803000210000030100
402047004240102301021000030103100031859446694013401063021210004602242000803000210000030100
402047004240102301021000030103100161859762699103401513025110018602202000803000310000030100
402047004040102301021000030103100031859392693993401063021210004602242000803000210000030100
402047004040102301021000030103100031859392693993401063021210004602242000803000210000030100
402047004340102301021000030103100151860007694210401503025110017602242000803000210000030100
402047004040102301021000030103100031859350693828401063021010004602242000803000210000030100
402047004040102301021000030103100031859392693993401063021210004602242000803000210000030100
402047004040102301021000030103100031859392693993401063021210004602242000803000210000030100
402057007040110301081000230135100031859392693993401063021210004602242000803000210000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570163400183001710001300401000318596716947384001630032100046002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018597336947474001030020100006002020000300031000030010
4002470047400133001310000300101000018614346954404001030020100006002020000300031000030010
4002470062400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002570160400223002010002300451000018597336947444001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  ldrsw x0, [x6, w7, sxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205401808013310180032100800083002562628010820080012200160024180000100
80204400578010110180000100800083006402688010820080012200160024180000100
80205401098013810180037100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100
80204400568010110180000100800083006402688010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025402498004111800301080000303202388001020800002016000018000010
80024400588001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080059305426738006920800712016000018000010
80024400638001111800001080000306403288001020800002016000018000010