Icestorm: LDRH (pre-index) measurements

Code:

  ldrh w0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1254	2036	1020	1016	1040	1000	21359	18344	2000	1000	1000	1000	1000	1001	1000	1000
2004	1124	2001	1001	1000	1000	1000	22516	19880	2000	1000	1000	1000	1000	1001	1000	1000
2004	1167	2001	1001	1000	1000	1000	21985	19294	2000	1000	1000	1000	1000	1001	1000	1000
2004	1190	2001	1001	1000	1000	1000	22838	19334	2000	1000	1000	1000	1000	1001	1000	1000
2004	1134	2001	1001	1000	1000	1000	23374	19639	2000	1000	1000	1000	1000	1001	1000	1000
2004	1163	2001	1001	1000	1000	1000	21986	18797	2000	1000	1000	1000	1000	1001	1000	1000
2004	1190	2001	1001	1000	1000	1000	22277	19502	2000	1000	1000	1000	1000	1001	1000	1000
2004	1182	2001	1001	1000	1000	1000	22364	19273	2000	1000	1000	1000	1000	1001	1000	1000
2004	1188	2001	1001	1000	1000	1000	22759	19656	2000	1000	1000	1000	1000	1001	1000	1000
2004	1196	2001	1001	1000	1000	1000	22703	19451	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrh w0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0110

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50209	71225	50161	40156	10005	40247	10003	1850609	534835	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70253	50103	40103	10000	40106	10003	1851446	535120	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70106	50103	40103	10000	40106	10003	1850361	534797	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70106	50103	40103	10000	40106	10013	1851965	535281	50153	40253	10015	70221	10004	40004	10000	0	40100
50204	70106	50103	40103	10000	40106	10003	1850361	534797	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70106	50103	40103	10000	40106	10003	1851306	535107	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70106	50103	40103	10000	40106	10003	1850307	534779	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70106	50103	40103	10000	40106	10003	1850307	534779	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70106	50103	40103	10000	40106	10003	1850307	534779	50109	40212	10004	70221	10004	40003	10000	0	40100
50204	70106	50103	40103	10000	40106	10003	1850361	534797	50109	40212	10004	70221	10004	40003	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0166

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50029	71228	50069	40064	10005	40156	10003	1852125	535668	50019	40032	10004	70020	10000	40007	10000	40010
50025	70261	50031	40029	10002	40050	10000	1851875	535567	50010	40020	10000	70020	10000	40008	10000	40010
50024	70160	50017	40017	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70158	50017	40017	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70169	50017	40017	10000	40010	10000	1853225	536017	50010	40020	10000	70020	10000	40008	10000	40010
50024	70174	50017	40017	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70158	50017	40017	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70170	50018	40018	10000	40010	10000	1851875	535567	50010	40020	10000	70020	10000	40007	10000	40010
50024	70160	50017	40017	10000	40010	10000	1851821	535549	50010	40020	10000	70109	10013	40018	10000	40010
50024	70160	50017	40017	10000	40010	10000	1851821	535549	50010	40020	10000	70020	10000	40008	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrh w0, [x6, #8]!
  ldrh w0, [x7, #8]!
  ldrh w0, [x8, #8]!
  ldrh w0, [x9, #8]!
  ldrh w0, [x10, #8]!
  ldrh w0, [x11, #8]!
  ldrh w0, [x12, #8]!
  ldrh w0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44240	160414	80313	80101	80316	80012	240610	641329	160124	80212	80012	80212	80012	80009	80000	80100
160204	43236	160109	80109	80000	80112	80012	240610	642959	160124	80212	80012	80212	80012	80009	80000	80100
160204	43237	160109	80109	80000	80112	80010	240610	643787	160122	80212	80012	80212	80012	80009	80000	80100
160204	43235	160109	80109	80000	80112	80011	240610	639236	160123	80212	80012	80254	80054	80051	80000	80100
160204	43236	160105	80105	80000	80108	80012	240623	639459	160124	80212	80012	80212	80012	80009	80000	80100
160204	43236	160109	80109	80000	80112	80008	240610	641872	160120	80212	80012	80212	80012	80009	80000	80100
160204	43231	160109	80109	80000	80112	80008	240654	645503	160120	80212	80012	80212	80012	80009	80000	80100
160204	43232	160109	80109	80000	80112	80010	240660	645394	160122	80212	80012	80212	80012	80009	80000	80100
160204	43230	160109	80109	80000	80112	80010	240610	644664	160122	80212	80012	80212	80012	80009	80000	80100
160204	43235	160109	80109	80000	80112	80011	240642	643178	160123	80212	80012	80212	80012	80009	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44536	160326	80222	80104	80225	80010	240340	643819	160032	80032	80012	80020	80000	80001	80000	80010
160024	43234	160011	80011	80000	80010	80000	240304	642241	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	643207	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	644049	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	645247	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	644469	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	641534	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	643586	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	645554	160010	80020	80000	80020	80000	80001	80000	80010
160024	43231	160011	80011	80000	80010	80000	240304	644469	160010	80020	80000	80020	80000	80001	80000	80010

LDRH (pre-index)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations