Icestorm: ASR (register, 64-bit) measurements

Code:

  asr x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25603	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  asr x0, x0, x1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	259330	10107	10214	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10025	10060	10035	10035	10069	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Code:

  asr x0, x1, x0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	259329	10107	10214	20228	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100
10204	10030	10101	10101	10107	259539	10107	10212	20224	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	259474	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	259591	10020	10020	20020	10011	10010

Test 4: throughput

Count: 8

Code:

  asr x0, x8, x9
  asr x1, x8, x9
  asr x2, x8, x9
  asr x3, x8, x9
  asr x4, x8, x9
  asr x5, x8, x9
  asr x6, x8, x9
  asr x7, x8, x9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	26860	80115	80115	80120	240360	80120	80222	160244	80015	80100
80204	26740	80114	80114	80119	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	160248	80015	80100
80204	26740	80114	80114	80119	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	160248	80015	80100
80204	26737	80115	80115	80120	240360	80120	80224	160248	80015	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	27981	80039	80039	80044	264148	80043	80046	160020	80011	80010
80024	26783	80021	80021	80020	277404	80020	80020	160020	80011	80010
80024	26717	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26717	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26717	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26717	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26717	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26717	80021	80021	80020	282738	80020	80020	160020	80011	80010
80024	26717	80021	80021	80020	263684	80098	80102	160020	80011	80010
80024	26723	80021	80021	80020	277404	80020	80020	160020	80011	80010

ASR (register, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations