Icestorm: NGCS (register, 32-bit) measurements

Code:

  ngcs w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  ngcs w0, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10107	251533	10109	10210	20216	10001	10100
10204	10030	10101	10101	10106	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251787	10147	10248	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10106	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253292	10028	10030	20122	10025	10010
10024	10030	10021	10021	10028	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	20020	10011	10010

Test 3: Latency 1->3

Chain cycles: 1

Code:

  ngcs w0, w1
  tst x0, 1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20201	20201	20208	509055	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100
20204	20030	20201	20201	20208	509018	20208	20208	30212	20101	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20021	20021	20028	0	509965	0	0	20031	20032	0	0	30020	20011	10010
20024	20030	20021	20021	20020	0	509904	0	0	20020	20020	0	0	30020	20011	10010
20024	20030	20021	20021	20020	0	509904	0	0	20020	20020	0	0	30020	20011	10010
20024	20030	20021	20021	20020	0	509904	0	0	20020	20020	0	0	30020	20011	10010
20024	20030	20021	20021	20020	0	509904	0	0	20020	20020	0	0	30020	20011	10010
20024	20030	20021	20021	20020	0	509904	0	0	20020	20020	0	0	30020	20011	10010
20024	20030	20021	20021	20020	0	509904	0	0	20020	20020	0	0	30038	20011	10010
20024	20030	20021	20021	20020	4220	588347	37166	562	29477	27390	5045	46	30020	20011	10010
20024	20030	20021	20021	20031	0	509782	0	0	20020	20020	0	0	30020	20011	10010
20024	20030	20021	20021	20020	0	509904	0	0	20020	20020	0	0	30020	20011	10010

Test 4: Latency 3->2

Chain cycles: 1

Code:

  ngcs w0, w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20108	519339	20108	20216	30221	20001	20100
20204	20030	20101	20101	20107	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20018	519454	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	20010

Test 5: Latency 3->3

Code:

  ngcs w0, w1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10210	253262	10208	10208	20228	10101	10100
10204	10030	10201	10201	10208	253318	10210	10210	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100
10204	10030	10201	10201	10208	253432	10208	10208	20216	10101	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10030	253235	10029	10032	20044	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010
10024	10030	10021	10021	10020	253383	10020	10020	20020	10011	10010

Test 6: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  ngcs w0, w8
  ands xzr, xzr, xzr
  ngcs w1, w8
  ands xzr, xzr, xzr
  ngcs w2, w8
  ands xzr, xzr, xzr
  ngcs w3, w8
  ands xzr, xzr, xzr
  ngcs w4, w8
  ands xzr, xzr, xzr
  ngcs w5, w8
  ands xzr, xzr, xzr
  ngcs w6, w8
  ands xzr, xzr, xzr
  ngcs w7, w8

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7992

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160205	63903	160145	160145	160155	0	681921	0	0	160113	160214	0	0	160218	160013	80100
160204	63502	160115	160115	160120	0	682134	0	0	160113	160214	0	0	160214	160009	80100
160204	63892	160112	160112	160118	0	681997	0	0	160116	160216	0	0	160220	160011	80100
160204	63935	160115	160115	160119	0	654216	0	0	160116	160217	0	0	160220	160012	80100
160204	63934	160111	160111	160115	0	682185	0	0	160118	160218	0	0	160220	160015	80100
160204	63913	160113	160113	160119	0	682238	0	0	160115	160216	0	0	160220	160011	80100
160204	63924	160112	160112	160116	0	682170	0	0	160119	160220	0	0	160220	160013	80100
160204	63920	160110	160110	160115	0	682153	0	0	160115	160216	0	0	160220	160015	80100
160204	63939	160111	160111	160115	0	682330	0	0	160118	160220	0	0	160220	160011	80100
160204	63903	160111	160111	160115	0	682162	0	0	160115	160216	0	0	160220	160011	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7928

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	65260	160020	160020	160026	0	678908	0	0	160030	160042	0	0	160076	160048	80010
160024	63832	160023	160023	160028	0	658127	0	0	160010	160020	0	0	160020	160001	80010
160024	63414	160011	160011	160010	68746	2555989	1404383	93108	198699	166514	81400	1712	160042	160014	80010
160024	63598	160011	160011	160010	0	651616	0	0	160010	160020	0	0	160020	160001	80010
160024	63332	160011	160011	160010	0	651992	0	0	160010	160020	0	0	160020	160001	80010
160024	64034	160011	160011	160010	0	657941	0	0	160010	160020	0	0	160020	160001	80010
160024	63548	160011	160011	160010	0	655537	0	0	160010	160020	0	0	160020	160001	80010
160024	63465	160011	160011	160010	0	659312	0	0	160010	160020	0	0	160020	160001	80010
160024	63377	160011	160011	160010	0	655742	0	0	160064	160076	0	0	160020	160001	80010
160024	63339	160011	160011	160010	0	656581	0	0	160010	160020	0	0	160020	160001	80010

Test 7: throughput

Count: 4

Code:

  fcmp s0, s0
  ngcs w0, w4
  ngcs w1, w4
  ngcs w2, w4
  ngcs w3, w4

Initialization

  mov x4, 5
  mov x5, 6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6208

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24845	50104	40101	10003	40112	10004	308950	40013	50114	40211	10003	80226	20008	40002	40100
50204	24832	50104	40102	10002	40113	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309569	40046	50155	40244	10011	80222	20006	40003	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309224	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100
50204	24831	50104	40101	10003	40112	10004	309222	40017	50116	40212	10004	80224	20008	40001	40100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6197

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50024	24888	50014	40012	10002	0	40019	10003	309559	40000	50010	40020	10000	80114	0	20024	40028	0	0	40010
50024	24688	50011	40011	10000	0	40010	10000	311978	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010
50024	24789	50011	40011	10000	0	40010	10000	311976	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010
50024	24826	50016	40014	10002	0	40024	10004	311173	40017	50028	40034	10004	80020	0	20000	40001	0	0	40010
50024	24789	50011	40011	10000	0	40010	10000	309586	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010
50024	24789	50011	40011	10000	0	40010	10000	311976	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010
50024	24789	50011	40011	10000	0	40010	10000	311976	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010
50024	24789	50011	40011	10000	0	40010	10000	311976	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010
50024	24789	50011	40011	10000	0	40010	10000	311976	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010
50024	24789	50011	40011	10000	0	40010	10000	311978	40000	50010	40020	10000	80020	0	20000	40001	0	0	40010

Test 8: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  ngcs w0, w7
  ngcs w1, w7
  ngcs w2, w7
  ngcs w3, w7
  ngcs w4, w7
  ngcs w5, w7
  ngcs w6, w7

Initialization

  mov x7, 8
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5844

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40934	80106	80106	80114	0	540657	0	0	80116	80216	0	0	140228	0	0	80004	0	0	70100
80204	40922	80107	80107	80112	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	140286	0	0	80037	0	0	70100
80204	40915	80108	80108	80116	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100
80204	40904	80105	80105	80113	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100
80204	40905	80107	80107	80112	0	541028	0	0	80112	80212	0	0	140220	0	0	80007	0	0	70100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5839

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80025	41036	80060	80060	0	0	80078	0	545998	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542378	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010
80024	40876	80021	80021	0	0	80020	0	542624	80020	80020	140020	80011	70010

NGCS (register, 32-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 7: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 8: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations