Icestorm: SMNEGL measurements

Code:

  smnegl x0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000
1004	3030	1001	1001	1000	25856	1000	1000	2000	1001	1000

Test 2: Latency 1->2

Code:

  smnegl x0, w0, w1

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260150	10100	10206	20212	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10025	30060	10026	10026	10034	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	0	10011	0	0	10010

Test 3: Latency 1->3

Code:

  smnegl x0, w1, w0

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	30030	10101	10101	10100	260144	10100	10206	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100
10204	30030	10101	10101	10100	260156	10100	10208	20216	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	30030	10021	10021	10020	259907	10020	10020	20084	10016	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20145	10032	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010
10024	30030	10021	10021	10020	259916	10020	10020	20020	10011	10010

Test 4: throughput

Count: 8

Code:

  smnegl x0, w8, w9
  smnegl x1, w8, w9
  smnegl x2, w8, w9
  smnegl x3, w8, w9
  smnegl x4, w8, w9
  smnegl x5, w8, w9
  smnegl x6, w8, w9
  smnegl x7, w8, w9

Initialization

  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	80054	80104	80104	80105	240315	80105	80210	160220	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160280	80020	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	160224	80004	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	80057	80025	80025	80026	0	240078	0	80026	80034	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010
80024	80032	80021	80021	80020	0	240060	0	80020	80020	0	160020	80011	80010

SMNEGL

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations