Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CSETM (32-bit)

Test 1: uops

Code:

  csetm w0, hi
  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
1004533100110011000300010001000100010011000
1004374100110011000300010001000100010011000
1004364100110011000300010001000100010011000
1004364100110011000300010001000100010011000
1004364100110011000300010001000100010011000
1004364100110011000300010001000100010011000
1004364100110011000300010001000100010011000
1004371100110011000300010001000100010011000
1004364100110011000300010001000100010011000
1004364100110011000300010001000100010011000

Test 2: Latency 1->2

Chain cycles: 1

Code:

  csetm w0, hi
  tst x0, 1
  mov x0, 1

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204200302020120201202085191872020820216202162010110100
20204200302020120201202085193252020820216202162010110100
20204200302020120201202085194482020820216202162010110100
20204200302020120201202085194482020820216202162010110100
20204200302020120201202085194482020820216202162010110100
20204200302020120201202085194482020820216202162010110100
20204200302020120201202085194482020820216202162010110100
20204200302020120201202085194482020820216202162010110100
20204200302020120201202085194482020820216202162010110100
20204200302020120201202085194482020820216202162010110100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024200302002120021200285195002002920036200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010
20024200302002120021200205195912002020020200202001110010

Test 3: throughput

Count: 8

Code:

  csetm w0, hi
  csetm w1, hi
  csetm w2, hi
  csetm w3, hi
  csetm w4, hi
  csetm w5, hi
  csetm w6, hi
  csetm w7, hi
  mov x0, 0
  cmp x0, x0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.3342

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204269038011580115801202916348012080222802228001580100
80204267428011480114801192932368012080224802248001580100
80204267418011580115801202932368012080224802248001580100
80204267378011580115801202932368012080224802218001480100
80204267378011580115801202932368012080224802248001580100
80204267378011580115801202932368012080224802218001480100
80204267378011580115801202932368012080224802248001580100
80204267378011580115801202932368012080224802248001580100
80204267378011580115801202932368012080224802248001580100
80204267378011580115801202932368012080224802248001580100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.3340

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80024281128003880038800513095638004980050800208001180010
80024267948002180021800203894378002080020800208001180010
80024267198002180021800204267808002080020800208001180010
80024267198002180021800204267808002080020800208001180010
80024267198002180021800204267808002080020800208001180010
80024267198002180021800204267808002080020800208001180010
80024267198002180021800204267808002080020800208001180010
80025268168008280082801074267808002080020800208001180010
80024267268002180021800204267808002080020800208001180010
80024267198002180021800204267808002080020800208001180010