Icestorm: SETF16 measurements

Code:

  setf16 w1

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001
1004	1030	1001	1001	1000	25192	1000	1000	2000	1001

Test 2: Latency 2->1

Chain cycles: 1

Code:

  setf16 w1
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519076	20108	20214	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100
20204	20030	20101	20101	20108	519548	20108	20216	30224	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	20030	20011	20011	20018	519507	20017	20032	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010
20024	20030	20011	20011	20010	519598	20010	20020	30020	20001	10010

Test 3: Latency 2->2

Code:

  setf16 w0

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(non-fused SUB/CBNZ loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10201	10201	10212	254506	10211	10214	20228	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100
10204	10030	10201	10201	10208	254709	10208	10208	20216	10101	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10029	255236	10029	10032	20020	10011	10
10024	10030	10021	10021	10029	255236	10029	10032	20020	10011	10
10024	10030	10021	10021	10020	255191	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10
10024	10030	10021	10021	10020	255193	10020	10020	20020	10011	10

Test 4: throughput

Count: 8

Code:

  ands xzr, xzr, xzr
  setf16 w0
  ands xzr, xzr, xzr
  setf16 w0
  ands xzr, xzr, xzr
  setf16 w0
  ands xzr, xzr, xzr
  setf16 w0
  ands xzr, xzr, xzr
  setf16 w0
  ands xzr, xzr, xzr
  setf16 w0
  ands xzr, xzr, xzr
  setf16 w0
  ands xzr, xzr, xzr
  setf16 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.7889

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160204	63270	160112	160112	160118	690899	160118	160220	160220	160013	100
160204	63117	160118	160118	160124	688223	160119	160220	160220	160010	100
160204	63100	160110	160110	160115	689181	160120	160220	160216	160011	100
160204	63127	160112	160112	160118	688236	160118	160220	160220	160012	100
160204	63082	160112	160112	160118	687157	160117	160218	160224	160014	100
160204	63102	160113	160113	160118	690367	160117	160218	160220	160013	100
160204	63127	160112	160112	160118	687037	160118	160220	160220	160012	100
160204	63128	160111	160111	160116	690896	160118	160220	160220	160014	100
160204	63072	160114	160114	160120	687961	160118	160220	160224	160019	100
160205	63148	160154	160154	160160	688682	160117	160218	160220	160013	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.7880

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
160024	64410	160021	160021	160026	701941	160030	160040	160020	160001	10
160024	63208	160011	160011	160010	701734	160010	160020	160020	160001	10
160024	63031	160011	160011	160010	696929	160010	160020	160020	160001	10
160024	63036	160011	160011	160010	699834	160010	160020	160020	160001	10
160024	63069	160011	160011	160010	703146	160010	160020	160020	160001	10
160024	63031	160011	160011	160010	697562	160010	160020	160020	160001	10
160024	63012	160011	160011	160010	695565	160010	160020	160020	160001	10
160024	63026	160011	160011	160010	701470	160010	160020	160020	160001	10
160024	63058	160011	160011	160010	699657	160010	160020	160020	160001	10
160024	63048	160011	160011	160010	697092	160010	160020	160020	160001	10

Test 5: throughput

Count: 4

Code:

  fcmp s0, s0
  setf16 w0
  setf16 w0
  setf16 w0
  setf16 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5997

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50204	24059	50107	40104	10003	40114	10004	315398	40012	50112	40209	10003	80234	20010	40006	100
50204	23973	50107	40104	10003	40114	10004	315520	40017	50116	40212	10004	80224	20008	40002	100
50204	23979	50106	40103	10003	40109	10003	315132	40017	50116	40212	10004	80224	20008	40002	100
50204	23999	50105	40102	10003	40112	10004	314947	40017	50116	40212	10004	80218	20006	40003	100
50204	23967	50103	40101	10002	40109	10003	315987	40017	50116	40212	10004	80224	20008	40001	100
50204	23977	50103	40101	10002	40112	10004	315987	40017	50116	40212	10004	80218	20006	40003	100
50204	23987	50109	40105	10004	40116	10004	315132	40017	50116	40212	10004	80218	20006	40001	100
50204	23976	50105	40102	10003	40112	10004	315132	40017	50116	40212	10004	80218	20006	40001	100
50204	23967	50104	40101	10003	40112	10004	315987	40017	50116	40212	10004	80218	20006	40003	100
50204	23981	50106	40103	10003	40109	10003	315987	40017	50116	40212	10004	80218	20006	40001	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5998

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map simd uop (7e)	map int uop inputs (7f)	map simd uop inputs (81)	? int output thing (e9)	? int retires (ef)
50024	24065	50018	40015	10003	40024	10004	315923	40013	50022	40029	10003	80020	20000	40001	10
50024	24028	50011	40011	10000	40010	10000	315849	40000	50010	40020	10000	80020	20000	40001	10
50024	23956	50011	40011	10000	40010	10000	316143	40000	50010	40020	10000	80020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	315746	40000	50010	40020	10000	80020	20000	40001	10
50024	23993	50011	40011	10000	40010	10000	316115	40000	50010	40020	10000	80020	20000	40001	10
50024	23954	50011	40011	10000	40010	10000	316575	40000	50010	40020	10000	80020	20000	40001	10
50024	24009	50011	40011	10000	40010	10000	317239	40000	50010	40020	10000	80020	20000	40001	10
50024	23991	50011	40011	10000	40010	10000	316269	40000	50010	40020	10000	80020	20000	40001	10
50024	23954	50011	40011	10000	40010	10000	316317	40000	50010	40020	10000	80020	20000	40001	10
50024	23956	50011	40011	10000	40010	10000	316088	40000	50010	40020	10000	80020	20000	40001	10

Test 6: throughput

Count: 7

Code:

  ands xzr, xzr, xzr
  setf16 w0
  setf16 w0
  setf16 w0
  setf16 w0
  setf16 w0
  setf16 w0
  setf16 w0

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5568

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	39060	80107	80107	80116	0	548603	0	0	80119	80220	0	0	140220	80003	100
80204	39015	80112	80112	80120	0	550543	0	0	80108	80208	0	0	140220	80005	100
80204	38974	80104	80104	80114	0	550546	0	0	80111	80212	0	0	140228	80004	100
80204	38969	80105	80105	80114	0	549185	0	0	80108	80208	0	0	140214	80003	100
80204	39042	80105	80105	80111	0	548752	0	0	80119	80220	0	0	140228	80009	100
80204	38973	80103	80103	80111	0	550985	0	0	80108	80208	0	0	140228	80006	100
80204	38966	80104	80104	80108	0	549310	0	0	80150	80252	0	0	140214	80003	100
80204	38997	80108	80108	80116	0	549899	0	0	80111	80212	0	0	140234	80007	100
80204	38970	80103	80103	80108	0	550540	0	0	80117	80218	0	0	140228	80005	100
80204	38984	80105	80105	80114	0	548462	0	0	80114	80216	0	0	140220	80003	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5562

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	38957	80032	80032	0	80044	549380	80020	80020	140020	80011	10
80024	38912	80021	80021	0	80020	550668	80020	80020	140020	80011	10
80024	38981	80021	80021	0	80020	548107	80020	80020	140020	80011	10
80024	38945	80021	80021	0	80020	550649	80020	80020	140020	80011	10
80024	38924	80021	80021	0	80020	550737	80020	80020	140020	80011	10
80024	38904	80021	80021	0	80020	550668	80020	80020	140020	80011	10
80024	38962	80021	80021	0	80020	550337	80020	80020	140020	80011	10
80024	38972	80021	80021	0	80020	549159	80020	80020	140020	80011	10
80024	38968	80021	80021	0	80020	550332	80020	80020	140122	80050	10
80024	38887	80021	80021	0	80020	550251	80020	80020	140020	80011	10

SETF16

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->1

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations