Icestorm: LDRSW (register) measurements

Code:

  ldrsw x0, [x6, x7]

Initialization

  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	674	1027	1	1026	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000
1004	547	1001	1	1000	1000	8112	1000	1000	2000	1	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70288	40108	30107	10001	30130	10003	1859635	694083	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859398	693871	40106	30210	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40205	70170	40110	30108	10002	30135	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100
40204	70042	40102	30102	10000	30103	10003	1859446	694013	40106	30212	10004	60224	20008	30002	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70155	40018	30017	10001	30040	10003	1859677	693716	40016	30030	10004	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10015	1860070	693939	40060	30067	10017	60020	20000	30003	10000	30010
40024	70051	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70054	40013	30013	10000	30010	10000	1859760	694756	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010
40024	70049	40013	30013	10000	30010	10000	1859706	694734	40010	30020	10000	60020	20000	30003	10000	30010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, x7]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8

Initialization

  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40205	70150	40108	30107	10001	30130	10003	1859539	693896	40106	30210	10004	60298	20034	30009	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60300	20036	30011	10000	30100
40204	70054	40103	30103	10000	30103	10003	1859797	694149	40106	30212	10004	60224	20008	30003	10000	30100
40204	70057	40103	30103	10000	30103	10015	1860250	694310	40150	30251	10017	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10015	1859980	694200	40150	30251	10017	60224	20008	30003	10000	30100
40204	70049	40103	30103	10000	30103	10003	1859635	694083	40106	30212	10004	60224	20008	30003	10000	30100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
40025	70154	40018	30017	10001	30040	10003	1859575	693633	40016	30032	10004	60020	20000	30003	10000	30010
40024	70047	40013	30013	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010
40024	70040	40012	30012	10000	30010	10000	1859463	694644	40010	30020	10000	60020	20000	30002	10000	30010

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]
  ldrsw x0, [x6, x7]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80206	40311	80168	101	80067	100	80008	300	418264	80108	200	80012	200	160024	1	80000	100
80204	40059	80105	101	80004	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40048	80101	101	80000	100	80008	300	641006	80108	200	80012	202	160480	2	80000	100
80204	40082	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640160	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100
80204	40045	80101	101	80000	100	80008	300	640070	80108	200	80012	200	160024	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40336	80039	11	0	80028	10	0	80000	30	260756	80010	20	80000	20	160000	1	80000	10
80024	40050	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10
80024	40043	80011	11	0	80000	10	0	80000	30	640040	80010	20	80000	20	160000	1	80000	10

LDRSW (register)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations