Icestorm: STR (pre-index, 64-bit) measurements

Code:

  str x0, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1401	2059	1041	1018	1040	1000	4649	17749	2000	1000	2000	1001	1000
1004	1078	2001	1001	1000	1000	1000	4761	17551	2000	1000	2000	1001	1000
1004	1072	2001	1001	1000	1000	1000	4761	17515	2000	1000	2000	1001	1000
1004	1074	2001	1001	1000	1000	1000	4761	17497	2000	1000	2000	1001	1000
1004	1073	2001	1001	1000	1000	1000	4761	17551	2000	1000	2000	1001	1000
1004	1090	2001	1001	1000	1000	1000	4749	17479	2000	1000	2000	1001	1000
1004	1073	2001	1001	1000	1000	1000	4761	17533	2000	1000	2000	1001	1000
1004	1071	2001	1001	1000	1000	1000	4761	17839	2000	1000	2000	1001	1000
1004	1071	2001	1001	1000	1000	1000	4761	17551	2000	1000	2000	1001	1000
1004	1100	2001	1001	1000	1000	1000	4761	17515	2000	1000	2000	1001	1000

Test 2: Latency 2->2

Code:

  str x0, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0091

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	11254	20404	10314	10090	10314	10003	105656	170876	20109	200	10010	200	20020	10005	10000	100
10204	10096	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100
10204	10091	20104	10104	10000	10104	10002	43628	170881	20106	200	10008	200	20016	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0087

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11260	20306	10216	10090	10217	10002	101265	170832	20016	20	10008	20	20020	10001	10000	10
10024	10091	20011	10011	10000	10010	10000	43079	170785	20010	20	10000	20	20000	10001	10000	10
10024	10086	20011	10011	10000	10010	10000	42967	170875	20010	20	10000	20	20000	10001	10000	10
10024	10086	20011	10011	10000	10010	10000	43075	171163	20010	20	10000	20	20000	10001	10000	10
10024	10115	20011	10011	10000	10010	10000	42938	171181	20010	20	10000	20	20000	10001	10000	10
10024	10112	20011	10011	10000	10010	10000	43079	170965	20010	20	10000	20	20000	10001	10000	10
10024	10121	20011	10011	10000	10010	10000	43079	170785	20010	20	10000	20	20000	10001	10000	10
10024	10086	20011	10011	10000	10010	10000	43079	170803	20010	20	10000	20	20000	10001	10000	10
10024	10086	20011	10011	10000	10010	10000	43079	170803	20010	20	10000	20	20000	10001	10000	10
10024	10087	20011	10011	10000	10010	10000	43079	170803	20010	20	10000	20	20000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  str x0, [x6, #8]!
  str x0, [x7, #8]!
  str x0, [x8, #8]!
  str x0, [x9, #8]!
  str x0, [x10, #8]!
  str x0, [x11, #8]!
  str x0, [x12, #8]!
  str x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0011

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	80981	160401	80311	80090	80311	80002	240312	1360108	160106	200	80008	200	160016	80005	80000	100
80204	80053	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80205	80115	160154	80137	80017	80140	80002	240312	1360157	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80036	240425	1360597	160178	200	80050	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1359997	160106	200	80008	200	160016	80005	80000	100
80204	80045	160105	80105	80000	80104	80002	240312	1360069	160106	200	80008	200	160016	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	80970	160305	80215	80090	80214	80002	240042	1360211	160016	20	80008	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80035	240149	1360807	160085	20	80048	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10
80024	80056	160011	80011	80000	80010	80000	240030	1360205	160010	20	80000	20	160000	80001	80000	10

STR (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 2->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations