Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSB (register, uxtw, 32-bit)

Test 1: uops

Code:

  ldrsb w0, [x6, w7, uxtw]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10056541027110261000816610001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000
10045431001110001000804010001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
40206702734011630113100033016210003185943769383104010630210100040602202000803000310000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100
40204700404010230102100003010310003185939269399304010630212100040602242000803000210000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570164400183001710001300401000318596776937164001630030100046002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470056400133001310000300101000018597876947674001030020100006002020000300031000030010
4002570165400213001910002300451066018971827147074167131415107656002020000300031000030010
4002470052400133001310000300101000018597336947454001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010
4002470054400133001310000300101000018599496948334001030020100006002020000300031000030010
4002470049400133001310000300101000018597066947344001030020100006002020000300031000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsb w0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570152401083010710001301301000318595876939414010630210100046022020008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031001518601696942624015030247100176022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100
4020470049401033010310000301031000318596356940834010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570333400183001710001300401000318596236936964001630030100046002020000300031000030010
4002470047400133001310000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002570070400203001810002300451000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300031000030010
4002470043400123001210000300101000018597876947764001030020100006002020000300021000030010

Test 4: throughput

Count: 8

Code:

  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  ldrsb w0, [x6, w7, uxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205402188012510180024100800083002481908010820080012200160024180000100
80204400598010510180004100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100
80204400528010110180000100800083006401968010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025405198003711800261080008304002628001820800122016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306418948001020800002016000018000010
80024400728001111800001080000306403828001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010