Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
stxrb w0, w1, [x6] nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
mov x0, 0
(no loop instructions)
Retires (minus 70 nops): 1.000
Issues: 1.000
Integer unit issues: 0.001
Load/store unit issues: 1.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 71005 | 60292 | 1003 | 1 | 1002 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34389 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33895 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34554 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 34227 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33900 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33901 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33897 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
| 71004 | 33897 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2002 | 1 | 1000 |
| 71004 | 33904 | 1001 | 1 | 1000 | 1000 | 4000 | 1000 | 1000 | 2000 | 1 | 1000 |
Code:
stxrb w0, w1, [x6] add x6, x6, 2
(fused SUBS/B.cc loop)
Result (median cycles for code): 2.1167
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20206 | 21342 | 20200 | 10164 | 10036 | 10165 | 10005 | 35505 | 221847 | 20110 | 10205 | 10005 | 10205 | 20010 | 10004 | 10000 | 10100 |
| 20204 | 21120 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 224148 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21167 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 223701 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21119 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 224910 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21171 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 224429 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21126 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 223894 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21183 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 223219 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21015 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 225349 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21092 | 20103 | 10103 | 10000 | 10104 | 10004 | 35497 | 222308 | 20108 | 10204 | 10004 | 10204 | 20008 | 10003 | 10000 | 10100 |
| 20204 | 21130 | 20103 | 10103 | 10000 | 10104 | 10034 | 35833 | 224829 | 20168 | 10234 | 10034 | 10204 | 20008 | 10003 | 10000 | 10100 |
Result (median cycles for code): 2.1066
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 20026 | 21410 | 20106 | 10070 | 10036 | 10073 | 10004 | 35248 | 222651 | 20018 | 10024 | 10004 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21109 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222326 | 20010 | 10020 | 10000 | 10054 | 20068 | 10035 | 10000 | 10010 |
| 20024 | 21648 | 20204 | 10132 | 10072 | 10131 | 10000 | 35259 | 222814 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21053 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222423 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21053 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222277 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21058 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 221982 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21048 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 221807 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21017 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 221536 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21036 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 222146 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
| 20024 | 21006 | 20011 | 10011 | 10000 | 10010 | 10000 | 35259 | 221888 | 20010 | 10020 | 10000 | 10020 | 20000 | 10001 | 10000 | 10010 |
Code:
stxrb w0, w1, [x6]
mov x7, 8
(fused SUBS/B.cc loop)
Result (median cycles for code): 3.0047
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10205 | 20159 | 10119 | 101 | 10018 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10205 | 30087 | 10121 | 103 | 10018 | 102 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30054 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 529071 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30076 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30050 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528891 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30066 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528927 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528909 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
| 10204 | 30047 | 10101 | 101 | 10000 | 100 | 10000 | 300 | 528855 | 10100 | 200 | 10004 | 200 | 20008 | 1 | 10000 | 100 |
Result (median cycles for code): 3.0047
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 10025 | 20162 | 10029 | 11 | 10018 | 10 | 10000 | 30 | 528963 | 10010 | 20 | 10004 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528945 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |
| 10024 | 30047 | 10011 | 11 | 10000 | 10 | 10000 | 30 | 528855 | 10010 | 20 | 10000 | 20 | 20000 | 1 | 10000 | 10 |