Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

UMULL

Test 1: uops

Code:

  umull x0, w0, w1
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000
100430301001100110002585610001000200010011000

Test 2: Latency 1->2

Code:

  umull x0, w0, w1
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
102043003010101101011010026015010100102062021200100010010100
102043003010101101011010026025910114102282021600100010010100
102043003010101101011010026015610100102082021600100010010100
102043003010101101011010026015610100102082021600100010010100
102043003010101101011010026015610100102082021600100010010100
102043003010101101011010026015610100102082021600100010010100
102043003010101101011010026015610100102082021600100010010100
102043003010101101011010026015610100102082021600100010010100
102043003010101101011010026015610100102082021600100010010100
102043003010101101011010026015610100102082021600100010010100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10025300601002610026100342599161002010020200201001110010

Test 3: Latency 1->3

Code:

  umull x0, w1, w0
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204300301010110101101002601441010010206202121000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100
10204300301010110101101002601561010010208202161000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 3.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024300301002110021100202599071002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010
10024300301002110021100202599161002010020200201001110010

Test 4: throughput

Count: 8

Code:

  umull x0, w8, w9
  umull x1, w8, w9
  umull x2, w8, w9
  umull x3, w8, w9
  umull x4, w8, w9
  umull x5, w8, w9
  umull x6, w8, w9
  umull x7, w8, w9
  mov x8, 9
  mov x9, 10

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
80204800448010480104801050240315008010580210001602248000480100
80204800348010480104801050240315008010580210001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100
80204800348010480104801050240315008010580212001602248000480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
800248005780025800258002624006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600948003180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010
800248003280021800218002024006080020800201600208001180010