Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

CBNZ (taken)

Test 1: uops

Code:

  cbnz x0, .+4

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)
1004	9401	5306	5306	7182	4509	1503	1509	1003	1
1004	4082	1032	1032	1038	3000	1000	1000	1000	1
1004	2459	1001	1001	1000	3000	1000	1000	1000	1
1004	2503	1001	1001	1000	3000	1000	1000	1000	1
1004	2438	1001	1001	1000	3000	1000	1000	1000	1
1004	2805	1001	1001	1000	3000	1000	1000	1000	1
1004	2776	1001	1001	1000	3000	1000	1000	1000	1
1004	2618	1001	1001	1000	3000	1000	1000	1000	1
1004	2497	1001	1001	1000	3000	1000	1000	1000	1
1004	2738	1001	1001	1000	3000	1000	1000	1000	1

Test 2: throughput

Count: 8

Code:

  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4
  cbnz x0, .+4

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0616

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	94706	83319	83319	84731	240318	80106	80206	80225	1	100
80204	85835	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84906	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84896	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84902	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84899	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84899	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84902	80105	80105	80106	240447	80150	80250	80206	1	100
80204	84893	80105	80105	80106	240318	80106	80206	80206	1	100
80204	84923	80105	80105	80106	240318	80106	80206	80206	1	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 3.9612

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	358614	108673	108673	118886	240296	80099	80109	80037	1	10
80024	316874	80012	80012	80011	240033	80011	80021	80021	1	10
80025	316752	80015	80015	80015	240050	80017	80027	80021	1	10
80024	316745	80012	80012	80011	240033	80011	80021	80037	1	10
80025	316762	80027	80027	80033	240083	80028	80038	80021	1	10
80024	316861	80012	80012	80011	240033	80011	80021	80021	1	10
80025	316928	80029	80029	80031	240033	80011	80021	80021	1	10
80024	316572	80012	80012	80011	240053	80018	80028	80021	1	10
80025	316648	80030	80030	80034	240033	80011	80021	80021	1	10
80024	316577	80012	80012	80011	240033	80011	80021	80021	1	10