Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

PRFM (register, PLDL1KEEP)

Test 1: uops

Code:

  prfm pldl1keep, [x6]

Initialization

  mov x0, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1004	2064	1001	1	1000	1000	34230	1000	1000	1000	1	1000
1004	1993	1001	1	1000	1000	35410	1000	1000	1000	1	1000
1004	2113	1001	1	1000	1000	35590	1000	1000	1000	1	1000
1004	2113	1001	1	1000	1000	35634	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35642	1000	1000	1000	1	1000
1004	2114	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2143	1001	1	1000	1000	35656	1000	1000	1000	1	1000
1004	2145	1001	1	1000	1000	35538	1000	1000	1000	1	1000
1004	2146	1001	1	1000	1000	35686	1000	1000	1000	1	1000
1004	2122	1001	1	1000	1000	35686	1000	1000	1000	1	1000

Test 2: throughput

Code:

  prfm pldl1keep, [x6]
  add x6, x6, 64

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0217

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20204	20796	20103	10103	10000	10108	10000	60863	350557	20103	10205	10005	10204	10004	10001	10000	10100
20204	19996	20106	10106	10000	10112	10000	61317	349929	20100	10202	10002	10204	10004	10003	10000	10100
20204	20141	20106	10106	10000	10112	10000	61212	350269	20104	10206	10006	10204	10004	10001	10000	10100
20204	20291	20102	10102	10000	10104	10000	61261	353369	20106	10208	10008	10208	10008	10002	10000	10100
20204	20098	20105	10105	10000	10110	10000	61417	350983	20102	10204	10004	10208	10008	10005	10000	10100
20204	20230	20102	10102	10000	10106	10000	61293	350869	20100	10202	10002	10210	10010	10003	10000	10100
20204	20068	20105	10105	10000	10110	10006	61735	346851	20118	10214	10014	10206	10006	10002	10000	10100
20204	20116	20102	10102	10000	10106	10031	61310	350253	20170	10241	10039	10203	10003	10002	10000	10100
20204	20195	20102	10102	10000	10104	10000	61169	352009	20102	10204	10004	10208	10008	10005	10000	10100
20204	20215	20102	10102	10000	10106	10000	60973	350189	20106	10208	10008	10202	10002	10001	10000	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0054

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
20024	20949	20015	10015	10000	10020	10000	61289	349761	20010	10020	10000	10020	10000	10001	10000	10010
20024	20167	20011	10011	10000	10010	10000	61025	351353	20010	10020	10000	10020	10000	10001	10000	10010
20024	20167	20011	10011	10000	10010	10000	61305	349615	20010	10020	10000	10020	10000	10001	10000	10010
20024	20096	20011	10011	10000	10010	10000	61294	350279	20010	10020	10000	10020	10000	10001	10000	10010
20024	20153	20011	10011	10000	10010	10000	60782	350575	20010	10020	10000	10020	10000	10001	10000	10010
20024	20115	20011	10011	10000	10010	10000	61257	350677	20010	10020	10000	10020	10000	10001	10000	10010
20024	20175	20011	10011	10000	10010	10000	61300	350369	20010	10020	10000	10020	10000	10001	10000	10010
20024	20192	20011	10011	10000	10010	10000	61069	351109	20010	10020	10000	10020	10000	10001	10000	10010
20024	20195	20011	10011	10000	10010	10000	61250	352485	20010	10020	10000	10020	10000	10001	10000	10010
20024	20170	20011	10011	10000	10010	10000	61158	351709	20010	10020	10000	10020	10000	10001	10000	10010

Test 3: throughput

Code:

  prfm pldl1keep, [x6]

Initialization

  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0503

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10204	20512	10101	101	10000	100	10002	300	357076	10102	200	10010	200	10010	1	10000	100
10204	20511	10101	101	10000	100	10000	300	356086	10100	200	10008	200	10012	1	10000	100
10205	20576	10131	101	10030	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20157	10101	101	10000	100	10000	300	357308	10100	200	10004	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10012	1	10000	100
10204	20503	10101	101	10000	100	10006	300	357346	10106	200	10012	200	10004	1	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0864

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10024	21137	10011	11	10000	10	10006	30	365438	10016	20	10012	20	10000	1	10000	10
10025	20935	10041	11	10030	10	10000	30	363966	10010	20	10000	20	10000	1	10000	10
10024	20916	10011	11	10000	10	10000	30	364494	10010	20	10000	20	10000	1	10000	10
10024	20869	10011	11	10000	10	10000	30	364702	10010	20	10000	20	10000	1	10000	10
10024	20818	10011	11	10000	10	10000	30	362654	10010	20	10000	20	10000	1	10000	10
10024	20765	10011	11	10000	10	10000	30	363322	10010	20	10000	20	10000	1	10000	10
10024	20874	10011	11	10000	10	10000	30	365374	10010	20	10000	20	10000	1	10000	10
10024	20960	10011	11	10000	10	10000	30	365330	10010	20	10000	20	10000	1	10000	10
10024	20963	10011	11	10000	10	10000	30	365330	10010	20	10000	20	10000	1	10000	10
10024	20960	10011	11	10000	10	10000	30	365322	10010	20	10000	20	10000	1	10000	10