Icestorm: SUBS (uxtw, 64-bit) measurements

Code:

  subs x0, x0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000
1004	2030	2001	2001	1000	52265	1000	1000	2000	2001	1000

Test 2: Latency 1->2

Code:

  subs x0, x0, w1, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529044	10104	10206	20212	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529192	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529607	10058	10068	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010

Test 3: Latency 1->3

Code:

  subs x0, x1, w0, uxtw

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	20030	20101	20101	10104	529026	10104	10206	20212	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20212	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100
10204	20030	20101	20101	10104	529087	10104	10208	20216	20001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	20030	20021	20021	10025	529192	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010
10024	20030	20021	20021	10020	529249	10020	10020	20020	20011	10010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, w2, uxtw
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20105	789233	20105	20212	30215	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	20015	789459	20015	20032	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, w2, uxtw
  cset x2, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	30030	30101	30101	20106	789233	20105	20212	30221	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100
20204	30030	30101	30101	20105	789712	20142	20255	30218	30001	20100
20204	30030	30101	30101	20105	789369	20105	20212	30218	30001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20024	30030	30011	30011	20015	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010
20024	30030	30011	30011	20010	789438	20010	20020	30020	30001	20010

Test 6: throughput

Count: 8

Code:

  subs x0, x8, w9, uxtw
  subs x1, x8, w9, uxtw
  subs x2, x8, w9, uxtw
  subs x3, x8, w9, uxtw
  subs x4, x8, w9, uxtw
  subs x5, x8, w9, uxtw
  subs x6, x8, w9, uxtw
  subs x7, x8, w9, uxtw

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	53408	160122	160122	80127	1099833	80127	80228	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100
80204	53404	160114	160114	80123	1100413	80164	80264	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100
80204	53404	160114	160114	80123	1100076	80123	80224	160248	160014	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	53395	160045	160045	80050	1104887	80050	80050	160076	160032	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160020	160011	80010
80025	53411	160087	160087	80088	1107732	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160076	160032	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160020	160011	80010
80024	53371	160021	160021	80020	1107732	80020	80020	160020	160011	80010

SUBS (uxtw, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 1->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: Latency 4->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 5: Latency 4->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 6: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations