Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

SUBS (uxtw, 64-bit)

Test 1: uops

Code:

  subs x0, x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 2.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000
100420302001200110005226510001000200020011000

Test 2: Latency 1->2

Code:

  subs x0, x0, w1, uxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290441010410206202122000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255291921002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205296071005810068200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010

Test 3: Latency 1->3

Code:

  subs x0, x1, w0, uxtw
  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10204200302010120101101045290261010410206202122000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202122000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100
10204200302010120101101045290871010410208202162000110100

1000 unrolls and 10 iterations

Result (median cycles for code): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
10024200302002120021100255291921002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010
10024200302002120021100205292491002010020200202001110010

Test 4: Latency 4->2

Chain cycles: 1

Code:

  subs x0, x1, w2, uxtw
  cset x1, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201057892332010520212302153000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157894592001520032300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 5: Latency 4->3

Chain cycles: 1

Code:

  subs x0, x1, w2, uxtw
  cset x2, cc
  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20204300303010130101201067892332010520212302213000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057893692010520212302183000120100
20204300303010130101201057897122014220255302183000120100
20204300303010130101201057893692010520212302183000120100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 2.0030

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
20024300303001130011200157894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010
20024300303001130011200107894382001020020300203000120010

Test 6: throughput

Count: 8

Code:

  subs x0, x8, w9, uxtw
  subs x1, x8, w9, uxtw
  subs x2, x8, w9, uxtw
  subs x3, x8, w9, uxtw
  subs x4, x8, w9, uxtw
  subs x5, x8, w9, uxtw
  subs x6, x8, w9, uxtw
  subs x7, x8, w9, uxtw
  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.6675

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8020453408160122160122801271099833801278022816024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100413801648026416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100
8020453404160114160114801231100076801238022416024816001480100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.6671

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)dispatch int uop (56)int uops in schedulers (59)dispatch uop (78)map int uop (7c)map int uop inputs (7f)? int output thing (e9)? int retires (ef)
8002453395160045160045800501104887800508005016007616003280010
8002453371160021160021800201107732800208002016002016001180010
8002553411160087160087800881107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016007616003280010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010
8002453371160021160021800201107732800208002016002016001180010