Icestorm: SUBS (immediate, 64-bit) measurements

Code:

  subs x0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	25043	1000	1000	1000	1001	1000

Test 2: Latency 1->2

Code:

  subs x0, x0, #3

Initialization

  mov x0, 1
  mov x1, 2

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10030	10101	10101	10108	251469	10108	10210	10210	10001	10100
10204	10030	10101	10101	10108	251676	10109	10210	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100
10204	10030	10101	10101	10108	251774	10108	10208	10208	10001	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10030	10021	10021	10028	253256	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	253161	10020	10020	10020	10011	10010

Test 3: Latency 3->2

Chain cycles: 1

Code:

  subs x0, x1, #3
  cset x1, cc

Initialization

  mov x0, 1
  mov x1, 2
  mov x2, 3
  mov x3, 4
  mov x4, 5

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
20204	20030	20101	20101	20107	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100
20204	20030	20101	20101	20108	519548	20108	20216	20216	20001	20100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 1 chain cycle): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
20024	20030	20011	20011	20018	519454	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519672	20054	20066	20299	0	0	20127	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010
20024	20030	20011	20011	20010	519598	20010	20020	20020	0	0	20001	0	0	20010

Test 4: throughput

Count: 8

Code:

  subs x0, x8, #3
  subs x1, x8, #3
  subs x2, x8, #3
  subs x3, x8, #3
  subs x4, x8, #3
  subs x5, x8, #3
  subs x6, x8, #3
  subs x7, x8, #3

Initialization

  mov x8, 9
  mov x9, 10
  mov x10, 11

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5010

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80204	40111	80109	80109	0	0	80112	0	240345	80115	80216	80216	0	0	80012	0	0	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	0	0	80012	0	0	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	0	0	80012	0	0	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	84576	2554	15	82017	1077	5	82236
80204	40081	80112	80112	0	0	80115	0	240435	80145	80245	80248	0	0	80040	0	0	80100
94199	65017	94493	89713	45	4735	89617	36	240345	80115	80216	80216	0	0	80012	0	0	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	0	0	80012	0	0	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	0	0	80012	0	0	80100
80205	40106	80140	80140	0	0	80147	0	240345	80115	80216	80216	0	0	80012	0	0	80100
80204	40081	80112	80112	0	0	80115	0	240345	80115	80216	80216	0	0	80012	0	0	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
80024	40161	80031	80031	80034	240110	80035	80036	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80025	40062	80061	80061	80068	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010
80024	40030	80021	80021	80020	240065	80020	80020	80020	0	0	80011	0	0	80010

SUBS (immediate, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 3->2

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations