Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

BFC (32-bit)

Test 1: uops

Code:

  bfc w0, #3, #7

Initialization

  mov x0, 1

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 1.001

Load/store unit issues: 0.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000
1004	1030	1001	1001	1000	3000	1000	1000	1000	1001	1000

Test 2: Latency 1->1

Code:

  bfc w0, #3, #7

Initialization

  mov x0, 1

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0034

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10204	10054	10104	10104	10105	30315	10105	10212	10212	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	10212	10004	10100
10205	10064	10118	10118	10122	30315	10105	10212	10212	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	10212	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	10212	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	10212	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	10212	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	10212	10004	10100
10204	10034	10104	10104	10105	30315	10105	10212	10212	10004	10100
10204	10054	10104	10104	10105	30315	10105	10212	10212	10004	10100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0030

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
10024	10035	10025	10025	10026	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010
10024	10030	10021	10021	10020	30060	10020	10020	10020	10011	10010

Test 3: throughput

Count: 8

Code:

  bfc w0, #3, #7
  bfc w1, #3, #7
  bfc w2, #3, #7
  bfc w3, #3, #7
  bfc w4, #3, #7
  bfc w5, #3, #7
  bfc w6, #3, #7
  bfc w7, #3, #7

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	dispatch int uop (56)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80204	80044	80104	80104	80105	240315	80105	80210	80210	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100
80205	80064	80118	80118	80122	240315	80105	80212	80212	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100
80204	80034	80104	80104	80105	240315	80105	80212	80212	80004	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	int uops in schedulers (59)	dispatch uop (78)	map int uop (7c)	map int uop inputs (7f)	? int output thing (e9)	? int retires (ef)
80024	80035	80025	80025	0	0	80026	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80056	80029	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010
80024	80030	80021	80021	0	0	80020	0	240060	80020	80020	80020	80011	80010