Icestorm: STP (pre-index, 64-bit) measurements

Code:

  stp x0, x1, [x6, #8]!

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
1005	1929	2059	1041	1018	1040	1000	4665	18539	2000	1000	3000	1001	1000
1004	1104	2001	1001	1000	1000	1000	4665	17775	2000	1000	3000	1001	1000
1004	1095	2001	1001	1000	1000	1000	4665	17803	2000	1000	3000	1001	1000
1004	1096	2001	1001	1000	1000	1000	4665	18305	2000	1000	3000	1001	1000
1004	1097	2001	1001	1000	1000	1000	4669	18451	2000	1000	3000	1001	1000
1004	1122	2001	1001	1000	1000	1000	4665	17894	2000	1000	3000	1001	1000
1004	1129	2001	1001	1000	1000	1000	4665	18798	2000	1000	3000	1001	1000
1004	1159	2001	1001	1000	1000	1000	4665	18803	2000	1000	3000	1001	1000
1004	1096	2001	1001	1000	1000	1000	4665	18195	2000	1000	3000	1001	1000
1004	1147	2001	1001	1000	1000	1000	4665	17749	2000	1000	3000	1001	1000

Test 2: Latency 3->3

Code:

  stp x0, x1, [x6, #8]!

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code): 1.0620

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10209	12022	20397	10307	10090	10307	10002	44675	180226	20108	200	10010	200	30030	10005	10000	100
10204	10608	20104	10104	10000	10104	10002	43546	180391	20106	200	10008	200	30024	10004	10000	100
10204	10608	20104	10104	10000	10104	10002	43549	180481	20106	200	10008	200	30024	10004	10000	100
10204	10606	20104	10104	10000	10104	10002	43542	180391	20106	200	10008	200	30024	10004	10000	100
10204	10620	20104	10104	10000	10104	10002	43544	180193	20106	200	10008	200	30024	10004	10000	100
10204	10612	20104	10104	10000	10104	10002	43542	180283	20106	200	10008	200	30024	10004	10000	100
10204	10618	20104	10104	10000	10104	10002	43541	180643	20106	200	10008	200	30024	10004	10000	100
10204	10627	20104	10104	10000	10104	10002	43549	180211	20106	200	10008	200	30024	10004	10000	100
10204	10633	20104	10104	10000	10104	10002	43542	180589	20106	200	10008	200	30024	10004	10000	100
10204	10632	20104	10104	10000	10104	10002	43544	180319	20106	200	10008	200	30024	10004	10000	100

1000 unrolls and 10 iterations

Result (median cycles for code): 1.0605

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
10029	11819	20311	10221	10090	10222	10002	42985	179941	20016	20	10008	20	30000	10001	10000	10
10024	10596	20011	10011	10000	10010	10000	42970	180295	20010	20	10000	20	30000	10001	10000	10
10024	10617	20011	10011	10000	10010	10000	42971	180079	20010	20	10000	20	30000	10001	10000	10
10024	10604	20011	10011	10000	10010	10000	42975	180421	20010	20	10000	20	30144	10036	10000	10
10024	10624	20011	10011	10000	10010	10000	42975	179683	20010	20	10000	20	30024	10004	10000	10
10024	10592	20011	10011	10000	10010	10000	42926	179461	20010	20	10000	20	30000	10001	10000	10
10024	10593	20011	10011	10000	10010	10000	42928	180379	20010	20	10000	20	30000	10001	10000	10
10024	10627	20011	10011	10000	10010	10000	42951	180055	20010	20	10000	20	30000	10001	10000	10
10024	10605	20011	10011	10000	10010	10000	42951	180397	20010	20	10000	20	30000	10001	10000	10
10024	10614	20011	10011	10000	10010	10000	42949	180379	20010	20	10000	20	30000	10001	10000	10

Test 3: throughput

Count: 8

Code:

  stp x0, x1, [x6, #8]!
  stp x0, x1, [x7, #8]!
  stp x0, x1, [x8, #8]!
  stp x0, x1, [x9, #8]!
  stp x0, x1, [x10, #8]!
  stp x0, x1, [x11, #8]!
  stp x0, x1, [x12, #8]!
  stp x0, x1, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0135

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80209	82006	160398	80308	80090	80308	80002	240312	1378612	160106	200	80008	200	240120	80033	80000	100
80204	81083	160106	80106	80000	80106	80002	240312	1378501	160106	200	80008	200	240024	80005	80000	100
80204	81083	160105	80105	80000	80104	80002	240312	1378661	160106	200	80008	200	240024	80005	80000	100
80204	81081	160105	80105	80000	80104	80002	240312	1378591	160106	200	80008	200	240024	80005	80000	100
80204	81073	160105	80105	80000	80104	80002	240312	1378697	160106	200	80008	200	240024	80005	80000	100
80204	81073	160105	80105	80000	80104	80002	240312	1378661	160106	200	80008	200	240024	80005	80000	100
80204	81083	160105	80105	80000	80104	80002	240312	1378519	160106	200	80008	200	240024	80005	80000	100
80682	85528	160625	80442	80183	80396	80002	240312	1378841	160106	200	80008	200	240024	80005	80000	100
80204	81072	160105	80105	80000	80104	80002	240312	1378483	160106	200	80008	200	240144	80037	80000	100
80204	81104	160105	80105	80000	80104	80002	240312	1378501	160106	200	80008	200	240024	80005	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0137

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80029	81926	160305	80215	80090	80214	80002	240042	1378985	160016	20	80008	20	240000	80001	80000	10
80024	81099	160011	80011	80000	80010	80000	240030	1378979	160010	20	80000	20	240000	80001	80000	10
80025	81200	160060	80043	80017	80046	80000	240030	1378979	160010	20	80000	20	240000	80001	80000	10
80024	81099	160011	80011	80000	80010	80000	240030	1378979	160010	20	80000	20	240000	80001	80000	10
80024	81099	160011	80011	80000	80010	80000	240030	1378979	160010	20	80000	20	240000	80001	80000	10
80024	81099	160011	80011	80000	80010	80000	240030	1378979	160010	20	80000	20	240000	80001	80000	10
80024	81099	160011	80011	80000	80010	80000	240030	1378979	160010	20	80000	20	240000	80001	80000	10
80024	81102	160011	80011	80000	80010	80000	240030	1379051	160010	20	80000	20	240000	80001	80000	10
80024	81099	160011	80011	80000	80010	80000	240030	1378979	160010	20	80000	20	240120	80033	80000	10
80024	81099	160011	80011	80000	80010	80000	240030	1378979	160010	20	80000	20	240000	80001	80000	10

STP (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 3->3

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations