Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LDRSW (register, uxtw)

Test 1: uops

Code:

  ldrsw x0, [x6, w7, uxtw]
  mov x7, #4
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
10058681031110301000816610001000200011000
10045431001110001000816610001000200011000
10045431001110001000825610001000200011000
10045431001110001000816610001000200011000
10045431001110001000816610001000200011000
10045431001110001000816610001000200011000
10045431001110001000816610001000200011000
10045431001110001000816610001000200011000
10045431001110001000816610001000200011000
10045431001110001000816610001000200011000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570154401083010710001301301000318594856938764010630210100046022020008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570157400183001710001300401000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470123400133001310000300101000018598686948024001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010
4002470047400133001310000300101000018596526947144001030020100006002020000300031000030010

Test 3: Latency 1->3 (with chain penalty)

Chain cycles: 3

Code:

  ldrsw x0, [x6, w7, uxtw]
  eor x8, x8, x0
  eor x8, x8, x0
  add x7, x7, x8
  mov x7, #4
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4020570156401083010710001301301000318594856938764010630210100046022020008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470055401033010310000301031001518600597074694015030248100176022420008300031000030100
4020470049401033010310000301031000318595816940634010630212100046022420008300041000030100
4020470052401033010310000301031000318597976941514010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100
4020470047401033010310000301031000318595816940634010630212100046022420008300031000030100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
4002570155400183001710001300401000018593676935394001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002570088400203001810002300451000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018594636946444001030020100006002020000300021000030010
4002470040400123001210000300101000018595176946664001030020100006002020000300021000030010

Test 4: throughput

Count: 8

Code:

  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  ldrsw x0, [x6, w7, uxtw]
  mov x7, 8

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205403828012110180020100800083004651428010820080012200160028180000100
80204400468010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160028180000100
80204400598010110180000100800083006403948010820080012200160594180000100
80204400528010110180000100800083006402148010820080012200160480180000100
80204400538010110180000100800083006401608010820080012200160024180000100
80204400458010110180000100800083006400708010820080012200160024180000100
80204400458010110180000100800083006401248010820080012200160024180000100
80204400508010110180000100800083006400708010820080012200160024180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025402328004511800341080008303202628001820800122016002818000010
80024400598001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024402898001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400548001111800001080000306402388001020800002016000018000010
80024400668001111800001080000306403468001020800002016000018000010