Icestorm: LDRSH (pre-index, 64-bit) measurements

Code:

  ldrsh x0, [x6, #8]!

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires: 2.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
2005	1221	2035	1020	1015	1038	1000	21162	17342	2000	1000	1000	1000	1000	1001	1000	1000
2004	1060	2001	1001	1000	1000	1000	21306	17543	2000	1000	1000	1000	1000	1001	1000	1000
2004	1074	2001	1001	1000	1000	1000	21481	17539	2000	1000	1000	1000	1000	1001	1000	1000
2004	1074	2001	1001	1000	1000	1000	21103	17538	2000	1000	1000	1000	1000	1001	1000	1000
2004	1098	2001	1001	1000	1000	1000	21401	17626	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21287	17579	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21381	17538	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21601	17556	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21141	18080	2000	1000	1000	1000	1000	1001	1000	1000
2004	1073	2001	1001	1000	1000	1000	21528	17560	2000	1000	1000	1000	1000	1001	1000	1000

Test 2: Latency 1->2 (with chain penalty)

Chain cycles: 3

Code:

  ldrsh x0, [x6, #8]!
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0110

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
50209	71233	50161	40156	10005	40247	10002	1850258	534710	50108	40211	10003	70221	10004	0	40004	10000	0	40100
50204	70092	50103	40103	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100
50204	70099	50104	40104	10000	40106	10013	1852289	535116	50153	40253	10015	70221	10004	0	40003	10000	0	40100
50204	70108	50104	40104	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100
50204	70099	50104	40104	10000	40106	10003	1850172	534716	50109	40212	10004	70221	10004	0	40004	10000	0	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 4.0138

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50030	71440	50079	40072	10007	40190	10003	1850883	535282	50019	40032	10004	70020	10000	40004	10000	40010
50024	70111	50014	40014	10000	40010	10000	1850444	535133	50010	40020	10000	70020	10000	40003	10000	40010
50024	70126	50013	40013	10000	40010	10000	1850984	535309	50010	40020	10000	70020	10000	40003	10000	40010
50024	70126	50013	40013	10000	40010	10000	1850417	535124	50010	40020	10000	70020	10000	40003	10000	40010
50024	70118	50013	40013	10000	40010	10000	1850849	535268	50010	40020	10000	70020	10000	40003	10000	40010
50024	70121	50013	40013	10000	40010	10012	1855164	536517	50062	40071	10014	70020	10000	40003	10000	40010
50024	70154	50013	40013	10000	40010	10000	1850903	535286	50010	40020	10000	70020	10000	40003	10000	40010
50024	70092	50013	40013	10000	40010	10012	1852111	535658	50062	40071	10013	70020	10000	40004	10000	40010
50024	70135	50013	40013	10000	40010	10000	1850687	535214	50010	40020	10000	70020	10000	40003	10000	40010
50024	70107	50013	40013	10000	40010	10000	1850903	535286	50010	40020	10000	70020	10000	40003	10000	40010

Test 3: throughput

Count: 8

Code:

  ldrsh x0, [x6, #8]!
  ldrsh x0, [x7, #8]!
  ldrsh x0, [x8, #8]!
  ldrsh x0, [x9, #8]!
  ldrsh x0, [x10, #8]!
  ldrsh x0, [x11, #8]!
  ldrsh x0, [x12, #8]!
  ldrsh x0, [x13, #8]!

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5404

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160209	44210	160418	80313	80105	80316	80009	240613	643812	160122	80213	80013	80212	80012	80009	80000	80100
160204	43236	160109	80109	80000	80112	80010	240610	643993	160122	80212	80012	80212	80012	80009	80000	80100
160204	43231	160110	80109	80001	80112	80011	240623	639479	160123	80212	80012	80210	80010	80007	80000	80100
160204	43230	160109	80109	80000	80112	80010	240610	637254	160122	80212	80012	80212	80012	80009	80000	80100
160204	43231	160109	80109	80000	80112	80011	240610	643781	160123	80212	80012	80212	80012	80009	80000	80100
160204	43229	160105	80105	80000	80108	80011	240610	645403	160123	80212	80012	80212	80012	80009	80000	80100
160204	43230	160109	80109	80000	80112	80011	240610	643084	160123	80212	80012	80212	80012	80009	80000	80100
160204	43230	160109	80109	80000	80112	80009	240610	650296	160121	80212	80012	80212	80012	80009	80000	80100
160204	43238	160113	80109	80004	80112	80054	241027	624899	160208	80254	80054	80212	80012	80009	80000	80100
160204	43230	160109	80109	80000	80112	80011	240610	635086	160123	80212	80012	80210	80010	80007	80000	80100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5403

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160029	44393	160337	80223	80114	80226	80000	240304	644702	160010	80020	80000	80020	80000	80001	80000	80010
160024	43230	160011	80011	80000	80010	80000	240223	644586	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	639398	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	645897	160010	80020	80000	80020	80000	80001	80000	80010
160024	43222	160011	80011	80000	80010	80000	240223	644680	160010	80020	80000	80020	80000	80001	80000	80010
160024	43221	160011	80011	80000	80010	80000	240223	645180	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	645038	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	643755	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	625363	160010	80020	80000	80020	80000	80001	80000	80010
160024	43223	160011	80011	80000	80010	80000	240223	646048	160010	80020	80000	80020	80000	80001	80000	80010

LDRSH (pre-index, 64-bit)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 (with chain penalty)

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations